hal_iq80310.h

移植到WLIT项目的redboot源代码

#define ATUDID_ADDR		0x00001202
#define PATUCMD_ADDR	0x00001204
#define PATUSR_ADDR		0x00001206
#define ATURID_ADDR		0x00001208
#define ATUCCR_ADDR		0x00001209
#define ATUCLSR_ADDR	0x0000120C
#define ATULT_ADDR		0x0000120D
#define ATUHTR_ADDR		0x0000120E
#define ATUBISTR_ADDR	0x0000120F
#define PIABAR_ADDR		0x00001210
/* Reserved 0x00001214 through 0x0000122B */
#define ASVIR_ADDR		0x0000122C
#define ASIR_ADDR		0x0000122E
#define ERBAR_ADDR		0x00001230
/* Reserved 0x00001234 */
/* Reserved 0x00001238 */
#define ATUILR_ADDR		0x0000123C
#define ATUIPR_ADDR		0x0000123D
#define ATUMGNT_ADDR	0x0000123E
#define ATUMLAT_ADDR	0x0000123F
#define PIALR_ADDR		0x00001240
#define PIATVR_ADDR		0x00001244
#define SIABAR_ADDR		0x00001248
#define SIALR_ADDR		0x0000124C
#define SIATVR_ADDR		0x00001250
#define POMWVR_ADDR		0x00001254
/* Reserved 0x00001258 */
#define POIOWVR_ADDR	0x0000125C
#define PODWVR_ADDR		0x00001260
#define POUDR_ADDR		0x00001264
#define SOMWVR_ADDR		0x00001268
#define SOIOWVR_ADDR	0x0000126C
/* Reserved 0x00001270 */
#define ERLR_ADDR		0x00001274
#define ERTVR_ADDR		0x00001278
/* Reserved 0x0000127C */
/* Reserved 0x00001280 */
/* Reserved 0x00001284 */
#define ATUCR_ADDR		0x00001288
/* Reserved 0x0000128C */
#define PATUISR_ADDR	0x00001290
#define SATUISR_ADDR	0x00001294
#define SATUCMD_ADDR	0x00001298
#define SATUSR_ADDR		0x0000129A
#define SODWVR_ADDR		0x0000129C
#define SOUDR_ADDR		0x000012A0
#define POCCAR_ADDR		0x000012A4
#define SOCCAR_ADDR		0x000012A8
#define POCCDR_ADDR		0x000012AC
#define SOCCDR_ADDR		0x000012B0
#define PAQCR_ADDR		0x000012B4
#define SAQCR_ADDR		0x000012B8
#define PAIMR_ADDR		0x000012BC
#define SAIMR_ADDR		0x000012C0
/* Reserved 0x000012C4 through 0x000012FF */

/* Messaging Unit 0000 1300H through 0000 130FH */
#define IMR0_ADDR		0x00001310
#define IMR1_ADDR		0x00001314
#define OMR0_ADDR		0x00001318
#define OMR1_ADDR		0x0000131C
#define IDR_ADDR		0x00001320
#define IISR_ADDR		0x00001324
#define IIMR_ADDR		0x00001328
#define ODR_ADDR		0x0000132C
#define OISR_ADDR		0x00001330
#define OIMR_ADDR		0x00001334
/* Reserved 0x00001338 through 0x0000134F */
#define MUCR_ADDR		0x00001350
#define QBAR_ADDR		0x00001354
/* Reserved 0x00001358 */
/* Reserved 0x0000135C */
#define IFHPR_ADDR		0x00001360
#define IFTPR_ADDR		0x00001364
#define IPHPR_ADDR		0x00001368
#define IPTPR_ADDR		0x0000136C
#define OFHPR_ADDR		0x00001370
#define OFTPR_ADDR		0x00001374
#define OPHPR_ADDR		0x00001378
#define OPTPR_ADDR		0x0000137C
#define IAR_ADDR		0x00001380
/* Reserved 0x00001384 through 0x000013FF */

/* DMA Controller 0000 1400H through 0000 14FFH */
#define	CCR0_ADDR		0x00001400
#define CSR0_ADDR		0x00001404
/* Reserved 0x00001408 */
#define DAR0_ADDR		0x0000140C
#define NDAR0_ADDR		0x00001410
#define PADR0_ADDR		0x00001414
#define PUADR0_ADDR		0x00001418
#define LADR0_ADDR		0x0000141C
#define BCR0_ADDR		0x00001420
#define DCR0_ADDR		0x00001424
/* Reserved 0x00001428 through 0x0000143F */
#define CCR1_ADDR		0x00001440
#define CSR1_ADDR		0x00001444
/* Reserved 0x00001448 */
#define DAR1_ADDR		0x0000144C
#define NDAR1_ADDR		0x00001450
#define PADR1_ADDR		0x00001454
#define PUADR1_ADDR		0x00001458
#define LADR1_ADDR		0x0000145C
#define BCR1_ADDR		0x00001460
#define DCR1_ADDR		0x00001464
/* Reserved 0x00001468 through 0x0000147F */
#define CCR2_ADDR		0x00001480
#define CSR2_ADDR		0x00001484
/* Reserved 0x00001488 */
#define DAR2_ADDR		0x0000148C
#define NDAR2_ADDR		0x00001490
#define PADR2_ADDR		0x00001494
#define PUADR2_ADDR		0x00001498
#define LADR2_ADDR		0x0000149C
#define BCR2_ADDR		0x000014A0
#define DCR2_ADDR		0x000014A4
/* Reserved 0x000014A8 through 0x000014FF */

/* Memory Controller 0000 1500H through 0000 15FFH */
#define SDIR_ADDR		0x00001500
#define SDCR_ADDR		0x00001504
#define SDBR_ADDR		0x00001508
#define SBR0_ADDR		0x0000150C
#define SBR1_ADDR		0x00001510
#define SDPR0_ADDR		0x00001514
#define SDPR1_ADDR		0x00001518
#define SDPR2_ADDR		0x0000151C
#define SDPR3_ADDR		0x00001520
#define SDPR4_ADDR		0x00001524
#define SDPR5_ADDR		0x00001528
#define SDPR6_ADDR		0x0000152C
#define SDPR7_ADDR		0x00001530
#define ECCR_ADDR		0x00001534
#define ELOG0_ADDR		0x00001538
#define ELOG1_ADDR		0x0000153C
#define ECAR0_ADDR		0x00001540
#define ECAR1_ADDR		0x00001544
#define ECTST_ADDR		0x00001548
#define FEBR0_ADDR		0x0000154C
#define FEBR1_ADDR		0x00001550
#define FBSR0_ADDR		0x00001554
#define FBSR1_ADDR		0x00001558
#define FWSR0_ADDR		0x0000155C
#define FWSR1_ADDR		0x00001560
#define MCISR_ADDR		0x00001564
#define RFR_ADDR		0x00001568
/* Reserved 0x0000156C through 0x000015FF */

/* Arbitration Control Unit 0000 1600H through 0000 167FH */
#define IACR_ADDR		0x00001600
#define MLTR_ADDR		0x00001604
#define MTTR_ADDR		0x00001608
/* Reserved 0x0000160C through 0x0000163F */

/* Bus Interface Control Unit 0000 1640H through 0000 167FH */
#define BIUCR_ADDR		0x00001640
#define BIUISR_ADDR		0x00001644
/* Reserved 0x00001648 through 0x0000167F */

/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
#define ICR_ADDR		0x00001680
#define ISR_ADDR		0x00001684
#define ISAR_ADDR		0x00001688
#define IDBR_ADDR		0x0000168C
#define ICCR_ADDR		0x00001690
#define IBMR_ADDR		0x00001694
/* Reserved 0x00001698 through 0x000016FF */

/* PCI And Peripheral Interrupt Controller 0000 1700H through 0000 17FFH */
#define NISR_ADDR		0x00001700
#define X7ISR_ADDR		0x00001704
#define X6ISR_ADDR		0x00001708
#define PDIDR_ADDR		0x00001710		/* EAS inconsistent */
/* Reserved 0x00001714 through 0x0000177F */

/* Application Accelerator Unit 0000 1800H through 0000 18FFH */
#define ACR_ADDR		0x00001800
#define ASR_ADDR		0x00001804
#define ADAR_ADDR		0x00001808
#define ANDAR_ADDR		0x0000180C
#define SAR1_ADDR		0x00001810
#define SAR2_ADDR		0x00001814
#define SAR3_ADDR		0x00001818
#define SAR4_ADDR		0x0000181C
#define DAR_ADDR		0x00001820
#define ABCR_ADDR		0x00001824
#define ADCR_ADDR		0x00001828
#define SAR5_ADDR		0x0000182C
#define SAR6_ADDR		0x00001830
#define SAR7_ADDR		0x00001834
#define SAR8_ADDR		0x00001838

/* Reserved 0x0000183C through 0x000018FF */

#define X6ISR_REG ((cyg_uint32 *)X6ISR_ADDR)
#  define X6ISR_DIP0 0x01
#  define X6ISR_DIP1 0x02
#  define X6ISR_DIP2 0x04
#  define X6ISR_EMIP 0x10
#  define X6ISR_AAIP 0x20

#define X7ISR_REG ((cyg_uint32 *)X7ISR_ADDR)
#  define X7ISR_ISQC 0x02
#  define X7ISR_INDB 0x04
#  define X7ISR_BIST 0x08

#define NISR_REG ((cyg_uint32 *)NISR_ADDR)
#  define NISR_MCU  0x01    
#  define NISR_PATU 0x02
#  define NISR_SATU 0x04
#  define NISR_PBDG 0x08
#  define NISR_SBDG 0x10
#  define NISR_DMA0 0x20
#  define NISR_DMA1 0x40
#  define NISR_DMA2 0x80
#  define NISR_MU   0x100
#  define NISR_AAU  0x400
#  define NISR_BIU  0x800

#define PIRSR_REG ((cyg_uint32 *)PIRSR_ADDR)
#define IISR_REG  ((cyg_uint32 *)IISR_ADDR)
#define IIMR_REG  ((cyg_uint32 *)IIMR_ADDR)
#define OISR_REG  ((cyg_uint32 *)OISR_ADDR)
#define OIMR_REG  ((cyg_uint32 *)OIMR_ADDR)
#define EMISR_REG ((cyg_uint32 *)EMISR_ADDR)
#define ISR_REG   ((cyg_uint32 *)ISR_ADDR)
#define GTMR_REG  ((cyg_uint32 *)GTMR_ADDR)
#define ESR_REG   ((cyg_uint32 *)ESR_ADDR)
#define ADCR_REG  ((cyg_uint32 *)ADCR_ADDR)
#define ICR_REG   ((cyg_uint32 *)ICR_ADDR)
#define ATUCR_REG ((cyg_uint32 *)ATUCR_ADDR)

#define DCR0_REG ((cyg_uint32 *)DCR0_ADDR)
#define DCR1_REG ((cyg_uint32 *)DCR1_ADDR)
#define DCR2_REG ((cyg_uint32 *)DCR2_ADDR)

#define ECCR_REG ((cyg_uint32 *)ECCR_ADDR)
#define MCISR_REG ((cyg_uint32 *)MCISR_ADDR)
#define ELOG0_REG ((cyg_uint32 *)ELOG0_ADDR)
#define ELOG1_REG ((cyg_uint32 *)ELOG1_ADDR)
#define ECAR0_REG ((cyg_uint32 *)ECAR0_ADDR)
#define ECAR1_REG ((cyg_uint32 *)ECAR1_ADDR)

#define PATUISR_REG ((cyg_uint32 *)PATUISR_ADDR)
#define SATUISR_REG ((cyg_uint32 *)SATUISR_ADDR)
#define PBISR_REG   ((cyg_uint32 *)PBISR_ADDR)
#define SBISR_REG   ((cyg_uint32 *)SBISR_ADDR)
#define CSR0_REG    ((cyg_uint32 *)CSR0_ADDR)
#define CSR1_REG    ((cyg_uint32 *)CSR1_ADDR)
#define CSR2_REG    ((cyg_uint32 *)CSR2_ADDR)
#define IISR_REG    ((cyg_uint32 *)IISR_ADDR)
#define ASR_REG     ((cyg_uint32 *)ASR_ADDR)
#define BIUISR_REG  ((cyg_uint32 *)BIUISR_ADDR)

#define PATUSR_REG  ((cyg_uint32 *)PATUSR_ADDR)
#define SATUSR_REG  ((cyg_uint32 *)SATUSR_ADDR)
#define PSR_REG  ((cyg_uint32 *)PSR_ADDR)
#define SSR_REG  ((cyg_uint32 *)SSR_ADDR)


#define MEMBASE_DRAM 0xa0000000

/* primary PCI bus definitions */ 
#define PRIMARY_BUS_NUM		0
#define PRIMARY_MEM_BASE	0x80000000
#define PRIMARY_DAC_BASE	0x84000000
#define PRIMARY_IO_BASE		0x90000000
#define PRIMARY_MEM_LIMIT	0x83ffffff
#define PRIMARY_DAC_LIMIT	0x87ffffff
#define PRIMARY_IO_LIMIT	0x9000ffff

/* secondary PCI bus definitions */
#define	SECONDARY_BUS_NUM	1
#define SECONDARY_MEM_BASE	0x88000000
#define SECONDARY_DAC_BASE	0x8c000000
#define SECONDARY_IO_BASE	0x90010000
#define SECONDARY_MEM_LIMIT	0x8bffffff
#define SECONDARY_DAC_LIMIT	0x8fffffff
#define SECONDARY_IO_LIMIT	0x9001ffff

#ifndef __ASSEMBLER__
extern unsigned int _80312_EMISR;  // Only valid for PEC ISR
#endif


/*---------------------------------------------------------------------------*/
/* end of hal_iq80310.h                                                         */
#endif /* CYGONCE_HAL_IQ80310_H */