sa2sim_misc.c

移植到WLIT项目的redboot源代码

// Read the current value of the clock, returning the number of hardware
// "ticks" that have occurred (i.e. how far away the current value is from
// the start)

void hal_clock_read(cyg_uint32 *pvalue)
{
    register cyg_uint32 now;
    asm volatile (
        "mrc      p14,0,%0,c1,c0,0;" // read from CCNT
        : "=r"(now)
        :
        /*:*/
        );
    *pvalue = now - hal_clock_init_period;
}

#endif

// -------------------------------------------------------------------------

// Using FIQ via an ISR will probably not work, but the interrupt API can
// be used to mask, unmask and detect it.  Best only to use with VSR.

// This routine is called to respond to a hardware interrupt (IRQ).  It
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
    int sources, masks;

    asm volatile ( // read the interrupt source reg INTSRC into r2
        "mrc      p13,0,%0,c4,c0,0;"
        : "=r"(sources)
        : 
      /*:*/
        );
    asm volatile ( // read the interrupt control reg INTCTL into r3
        "mrc      p13,0,%0,c0,c0,0;"
        : "=r"(masks)
        : 
      /*:*/
        );
    // is a source both unmasked and active?
    if ( (0 != (1 & masks)) && (0 != ((8 << 28) & sources)) )
        return CYGNUM_HAL_INTERRUPT_NFIQ;
    if ( (0 != (2 & masks)) && (0 != ((4 << 28) & sources)) )
        return CYGNUM_HAL_INTERRUPT_NIRQ;
    if ( (0 != (8 & masks)) && (0 != ((2 << 28) & sources)) )
        return CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT;
    if ( (0 != (4 & masks)) && (0 != ((1 << 28) & sources)) ) {
        // more complicated; it's the PMU.
        asm volatile ( // read the PMNC perfmon control reg
            "mrc      p14,0,%0,c0,c0,0;"
            : "=r"(sources)
            : 
            /*:*/
            );
        // sources is now the PMNC performance monitor control register
        // enable bits are 4..6, status bits are 8..10
        sources = (sources >> 4) & (sources >> 8);
        if ( 1 & sources )
            return CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL;
        if ( 2 & sources )
            return CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL;
        if ( 4 & sources )
            return CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL;
    }

#if 0
    // WORKAOUND - limitation in the sim - external IRQs are not latching.
    // So INTSRC register can read zeros if IRQ is re-enabled late in the
    // actual asserted period.
    if ( 2 == masks )
        return CYGNUM_HAL_INTERRUPT_NIRQ;
#endif

    return CYGNUM_HAL_INTERRUPT_reserved0; // This shouldn't happen!
}

//
// Interrupt control
//

void hal_interrupt_mask(int vector)
{
    int mask = 0;
    int submask = 0;
    switch ( vector ) {
    case CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL:
        submask = vector - CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL; // 0 to 2
        // select interrupt enable bit and also enable the perfmon per se
        submask = (1 << (submask + 4)); // bits 4-6 are masks
        asm volatile (
            "mrc      p14,0,r1,c0,c0,0;"
            "bic      r1, r1, #0x700;" // clear the overflow/interrupt flags
            "bic      r1, r1, #0x006;" // clear the reset bits
            "bic      %0, r1, %0;"     // preserve r1; better for debugging
            "tsts     %0, #0x070;"     // are all 3 sources now off?
            "biceq    %0, %0, #1;"     // if so, disable entirely.
            "mcr      p14,0,%0,c0,c0,0;"
            :
            : "r"(submask)
            : "r1"
            );
        mask = 4;
        break;
    case CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT:
        // Nothing specific to do here
        mask = 8;
        break;
    case CYGNUM_HAL_INTERRUPT_NIRQ         :
        mask = 2;
        break;
    case CYGNUM_HAL_INTERRUPT_NFIQ         :
        mask = 1;
        break;
    default:
        /* do nothing */
        return;
    }
    asm volatile (
        "mrc      p13,0,r1,c0,c0,0;"
        "bic      r1, r1, %0;"
        "mcr      p13,0,r1,c0,c0,0;"
        :
        : "r"(mask)
        : "r1"
        );
}

void hal_interrupt_unmask(int vector)
{
    int mask = 0;
    int submask = 0;
    switch ( vector ) {
    case CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL:
        submask = vector - CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL; // 0 to 2
        // select interrupt enable bit and also enable the perfmon per se
        submask = 1 + (1 << (submask + 4)); // bits 4-6 are masks
        asm volatile (
            "mrc      p14,0,r1,c0,c0,0;"
            "bic      r1, r1, #0x700;"   // clear the overflow/interrupt flags
            "bic      r1, r1, #0x006;"   // clear the reset bits
            "orr      %0, r1, %0;"       // preserve r1; better for debugging
            "mcr      p14,0,%0,c0,c0,0;"
            "mrc      p13,0,r2,c8,c0,0;" // steer PMU interrupt to IRQ
            "and      r2, r2, #2;"       // preserve the other bit (BCU steer)
            "mcr      p13,0,r2,c8,c0,0;"
            :
            : "r"(submask)
            : "r1","r2"
            );
        mask = 4;
        break;
    case CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT:
         asm volatile (
            "mrc      p13,0,r2,c8,c0,0;" // steer BCU interrupt to IRQ
            "and      r2, r2, #1;"       // preserve the other bit (PMU steer)
            "mcr      p13,0,r2,c8,c0,0;"
            :
            : 
            : "r2"
            );
        mask = 8;
        break;
    case CYGNUM_HAL_INTERRUPT_NIRQ         :
        mask = 2;
        break;
    case CYGNUM_HAL_INTERRUPT_NFIQ         :
        mask = 1;
        break;
    default:
        /* do nothing */
        return;
    }
    asm volatile (
        "mrc      p13,0,r1,c0,c0,0;"
        "orr      %0, r1, %0;"
        "mcr      p13,0,%0,c0,c0,0;"
        :
        : "r"(mask)
        : "r1"
        );
}

void hal_interrupt_acknowledge(int vector)
{
    int submask = 0;
    switch ( vector ) {
    case CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL:
    case CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL:
        submask = vector - CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL; // 0 to 2
        // select interrupt enable bit and also enable the perfmon per se
        submask = (1 << (submask + 8)); // bits 8-10 are status; write 1 clr
        // Careful not to ack other interrupts or zero any counters:
        asm volatile (
            "mrc      p14,0,r1,c0,c0,0;"
            "bic      r1, r1, #0x700;" // clear the overflow/interrupt flags
            "bic      r1, r1, #0x006;" // clear the reset bits
            "orr      %0, r1, %0;"     // preserve r1; better for debugging
            "mcr      p14,0,%0,c0,c0,0;"
            :
            : "r"(submask)
            : "r1"
            );
        break;
    case CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT:
    case CYGNUM_HAL_INTERRUPT_NIRQ         :
    case CYGNUM_HAL_INTERRUPT_NFIQ         :
    default:
        /* do nothing */
        return;
    }
}

void hal_interrupt_configure(int vector, int level, int up)
{
    // No interrupts are configurable on this hardware
}

void hal_interrupt_set_level(int vector, int level)
{
    // No interrupts are configurable on this hardware
}

/*------------------------------------------------------------------------*/
// hal_default_isr is now provided by the hal_if.c file - which is not
// used when building for the sa2sim target, so we include a copy here.

externC cyg_uint32
hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
    CYG_TRACE1(true, "Interrupt: %d", vector);

    diag_printf("Spurious Interrupt!!! - vector: %d, data: %x\n", vector, 
                data);
    CYG_FAIL("Spurious Interrupt!!!");
    return 0;
}

/*------------------------------------------------------------------------*/
// EOF sa2sim_misc.c