bangirq.pil

来自「移植到WLIT项目的redboot源代码」· PIL 代码 · 共 38 行

// IRQ for 8 clocks every 330000 clocks

// MCLK clock is up to 100MHz; CPU clock CCLK is (by default) 3 x CLK and
// CLK seems to be the same as MCLK in the model.
// So if the clock is 33MHz, 100Hz is acquired with 330,000 ticks.

// But that takes ages, so we will use 1000Hz instead for our testing.
// That's slow enough so that spurious interrupts do not get into a loop.

period = 33000; // 1000Hz

//period = 300000000; // none, essentially

duration = 300; // enough time to sense and decode it!  [was 8]

bangIrq.value = 1;
bangIrq.duration = period - duration;

//print "Cycle: "; print cpu.cycle; print " }}}}}}}}}}}}} IRQ INITIALLY DE-ASSERTED\n";

bangIrq.endDuration
{
    if(bangIrq.value == 0)
    {
        bangIrq.value = 1;
        bangIrq.duration = period - duration;
//        print "Cycle: "; print cpu.cycle; print " }}}}}}}}}}}}} IRQ DE-ASSERTED\n";
    }
    else
    {
        bangIrq.value = 0;
        bangIrq.duration = duration;
//        print "Cycle: "; print cpu.cycle; print " {{{{{{{{{{{{{ IRQ ASSERTED\n";
    }
}