hal_sitsang.h

移植到WLIT项目的redboot源代码

#define FDADR1     ( 0x44000210 )          // DMA channel 1 frame descriptor address register
#define FSADR1     ( 0x44000214 )          // DMA channel 1 frame source address register
#define FIDR1      ( 0x44000218 )          // DMA channel 1 frame ID register
#define LDCMD1     ( 0x4400021C )          // DMA channel 1 command register
#define FBR0       ( 0x44000020 )          // DMA channel 0 frame branch register
#define FBR1       ( 0x44000024 )          // DMA channel 1 frame branch register
#define LCSR       ( 0x44000038 )          // LCD controller status register
#define LIIDR      ( 0x4400003C )          // LCD controller interrupt ID register
#define TRGBR      ( 0x44000040 )          // TMED RGB Seed Register
#define TCR        ( 0x44000044 )          // TMED Control Register
//     DMA Controller 0x40000000  
#define DCSR0      ( 0x40000000 )          // DMA Control / Status Register for Channel 0
#define DCSR1      ( 0x40000004 )          // DMA Control / Status Register for Channel 1
#define DCSR2      ( 0x40000008 )          // DMA Control / Status Register for Channel 2
#define DCSR3      ( 0x4000000c )          // DMA Control / Status Register for Channel 3
#define DCSR4      ( 0x40000010 )          // DMA Control / Status Register for Channel 4
#define DCSR5      ( 0x40000014 )          // DMA Control / Status Register for Channel 5
#define DCSR6      ( 0x40000018 )          // DMA Control / Status Register for Channel 6
#define DCSR7      ( 0x4000001c )          // DMA Control / Status Register for Channel 7
#define DCSR8      ( 0x40000020 )          // DMA Control / Status Register for Channel 8
#define DCSR9      ( 0x40000024 )          // DMA Control / Status Register for Channel 9
#define DCSR10     ( 0x40000028 )          // DMA Control / Status Register for Channel 10
#define DCSR11     ( 0x4000002c )          // DMA Control / Status Register for Channel 11
#define DCSR12     ( 0x40000030 )          // DMA Control / Status Register for Channel 12
#define DCSR13     ( 0x40000034 )          // DMA Control / Status Register for Channel 13
#define DCSR14     ( 0x40000038 )          // DMA Control / Status Register for Channel 14
#define DCSR15     ( 0x4000003c )          // DMA Control / Status Register for Channel 15
#define DINT       ( 0x400000f0 )          // DMA Interrupt Register
#define DRCMR0     ( 0x40000100 )          // Request to Channel Map Register for DREQ 0 (companion chip request 0)
#define DRCMR1     ( 0x40000104 )          // Request to Channel Map Register for DREQ 1 (companion chip request 1)
#define DRCMR2     ( 0x40000108 )          // Request to Channel Map Register for I2S receive Request
#define DRCMR3     ( 0x4000010c )          // Request to Channel Map Register for I2S transmit Request
#define DRCMR4     ( 0x40000110 )          // Request to Channel Map Register for BTUART receive Request
#define DRCMR5     ( 0x40000114 )          // Request to Channel Map Register for BTUART transmit Request.
#define DRCMR6     ( 0x40000118 )          // Request to Channel Map Register for FFUART receive Request
#define DRCMR7     ( 0x4000011c )          // Request to Channel Map Register for FFUART transmit Request
#define DRCMR8     ( 0x40000120 )          // Request to Channel Map Register for AC97 microphone Request
#define DRCMR9     ( 0x40000124 )          // Request to Channel Map Register for AC97 modem receive Request
#define DRCMR10    ( 0x40000128 )          // Request to Channel Map Register for AC97 modem transmit Request
#define DRCMR11    ( 0x4000012c )          // Request to Channel Map Register for AC97 audio receive Request
#define DRCMR12    ( 0x40000130 )          // Request to Channel Map Register for AC97 audio transmit Request
#define DRCMR13    ( 0x40000134 )          // Request to Channel Map Register for SSP receive Request
#define DRCMR14    ( 0x40000138 )          // Request to Channel Map Register for SSP transmit Request
#define DRCMR15    ( 0x4000013c )          // Reserved
#define DRCMR16    ( 0x40000140 )          // Reserved
#define DRCMR17    ( 0x40000144 )          // Request to Channel Map Register for ICP receive Request
#define DRCMR18    ( 0x40000148 )          // Request to Channel Map Register for ICP transmit Request
#define DRCMR19    ( 0x4000014c )          // Request to Channel Map Register for STUART receive Request
#define DRCMR20    ( 0x40000150 )          // Request to Channel Map Register for STUART transmit Request
#define DRCMR21    ( 0x40000154 )          // Request to Channel Map Register for MMC receive Request
#define DRCMR22    ( 0x40000158 )          // Request to Channel Map Register for MMC transmit Request
#define DRCMR23    ( 0x4000015c )          // RESERVED
#define DRCMR24    ( 0x40000160 )          // RESERVED
#define DRCMR25    ( 0x40000164 )          // Request to Channel Map Register for USB endpoint 1 Request
#define DRCMR26    ( 0x40000168 )          // Request to Channel Map Register for USB endpoint 2 Request
#define DRCMR27    ( 0x4000016C )          // Request to Channel Map Register for USB endpoint 3 Request
#define DRCMR28    ( 0x40000170 )          // Request to Channel Map Register for USB endpoint 4 Request
#define DRCMR29    ( 0x40000174 )          // RESERVED
#define DRCMR30    ( 0x40000178 )          // Request to Channel Map Register for USB endpoint 6 Request
#define DRCMR31    ( 0x4000017C )          // Request to Channel Map Register for USB endpoint 7 Request
#define DRCMR32    ( 0x40000180 )          // Request to Channel Map Register for USB endpoint 8 Request
#define DRCMR33    ( 0x40000184 )          // Request to Channel Map Register for USB endpoint 9 Request
#define DRCMR34    ( 0x40000188 )          // RESERVED
#define DRCMR35    ( 0x4000018C )          // Request to Channel Map Register for USB endpoint 11 Request
#define DRCMR36    ( 0x40000190 )          // Request to Channel Map Register for USB endpoint 12 Request
#define DRCMR37    ( 0x40000194 )          // Request to Channel Map Register for USB endpoint 13 Request
#define DRCMR38    ( 0x40000198 )          // Request to Channel Map Register for USB endpoint 14 Request
#define DRCMR39    ( 0x4000019C )          // RESERVED
#define DDADR0     ( 0x40000200 )          // DMA Descriptor Address Register channel 0
#define DSADR0     ( 0x40000204 )          // DMA Source Address Register channel 0
#define DTADR0     ( 0x40000208 )          // DMA Target Address Register channel 0
#define DCMD0      ( 0x4000020C )          // DMA Command Address Register channel 0
#define DDADR1     ( 0x40000210 )          // DMA Descriptor Address Register channel 1
#define DSADR1     ( 0x40000214 )          // DMA Source Address Register channel 1
#define DTADR1     ( 0x40000218 )          // DMA Target Address Register channel 1
#define DCMD1      ( 0x4000021C )          // DMA Command Address Register channel 1
#define DDADR2     ( 0x40000220 )          // DMA Descriptor Address Register channel 2
#define DSADR2     ( 0x40000224 )          // DMA Source Address Register channel 2
#define DTADR2     ( 0x40000228 )          // DMA Target Address Register channel 2
#define DCMD2      ( 0x4000022C )          // DMA Command Address Register channel 2
#define DDADR3     ( 0x40000230 )          // DMA Descriptor Address Register channel 3
#define DSADR3     ( 0x40000234 )          // DMA Source Address Register channel 3
#define DTADR3     ( 0x40000238 )          // DMA Target Address Register channel 3
#define DCMD3      ( 0x4000023C )          // DMA Command Address Register channel 3
#define DDADR4     ( 0x40000240 )          // DMA Descriptor Address Register channel 4
#define DSADR4     ( 0x40000244 )          // DMA Source Address Register channel 4
#define DTADR4     ( 0x40000248 )          // DMA Target Address Register channel 4
#define DCMD4      ( 0x4000024C )          // DMA Command Address Register channel 4
#define DDADR5     ( 0x40000250 )          // DMA Descriptor Address Register channel 5
#define DSADR5     ( 0x40000254 )          // DMA Source Address Register channel 5
#define DTADR5     ( 0x40000258 )          // DMA Target Address Register channel 5
#define DCMD5      ( 0x4000025C )          // DMA Command Address Register channel 5
#define DDADR6     ( 0x40000260 )          // DMA Descriptor Address Register channel 6
#define DSADR6     ( 0x40000264 )          // DMA Source Address Register channel 6
#define DTADR6     ( 0x40000268 )          // DMA Target Address Register channel 6
#define DCMD6      ( 0x4000026C )          // DMA Command Address Register channel 6
#define DDADR7     ( 0x40000270 )          // DMA Descriptor Address Register channel 7
#define DSADR7     ( 0x40000274 )          // DMA Source Address Register channel 7
#define DTADR7     ( 0x40000278 )          // DMA Target Address Register channel 7
#define DCMD7      ( 0x4000027C )          // DMA Command Address Register channel 7
#define DDADR8     ( 0x40000280 )          // DMA Descriptor Address Register channel 8
#define DSADR8     ( 0x40000284 )          // DMA Source Address Register channel 8
#define DTADR8     ( 0x40000288 )          // DMA Target Address Register channel 8
#define DCMD8      ( 0x4000028C )          // DMA Command Address Register channel 8
#define DDADR9     ( 0x40000290 )          // DMA Descriptor Address Register channel 9
#define DSADR9     ( 0x40000294 )          // DMA Source Address Register channel 9
#define DTADR9     ( 0x40000298 )          // DMA Target Address Register channel 9
#define DCMD9      ( 0x4000029C )          // DMA Command Address Register channel 9
#define DDADR10    ( 0x400002a0 )          // DMA Descriptor Address Register channel 10
#define DSADR10    ( 0x400002a4 )          // DMA Source Address Register channel 10
#define DTADR10    ( 0x400002a8 )          // DMA Target Address Register channel 10
#define DCMD10     ( 0x400002aC )          // DMA Command Address Register channel 10
#define DDADR11    ( 0x400002b0 )          // DMA Descriptor Address Register channel 11
#define DSADR11    ( 0x400002b4 )          // DMA Source Address Register channel 11
#define DTADR11    ( 0x400002b8 )          // DMA Target Address Register channel 11
#define DCMD11     ( 0x400002bC )          // DMA Command Address Register channel 11
#define DDADR12    ( 0x400002c0 )          // DMA Descriptor Address Register channel 12
#define DSADR12    ( 0x400002c4 )          // DMA Source Address Register channel 12     
#define DTADR12    ( 0x400002c8 )          // DMA Target Address Register channel 12     
#define DCMD12     ( 0x400002cC )          // DMA Command Address Register channel 12     
#define DDADR13    ( 0x400002d0 )          // DMA Descriptor Address Register channel 13     
#define DSADR13    ( 0x400002d4 )          // DMA Source Address Register channel 13     
#define DTADR13    ( 0x400002d8 )          // DMA Target Address Register channel 13     
#define DCMD13     ( 0x400002dC )          // DMA Command Address Register channel 13     
#define DDADR14    ( 0x400002e0 )          // DMA Descriptor Address Register channel 14     
#define DSADR14    ( 0x400002e4 )          // DMA Source Address Register channel 14     
#define DTADR14    ( 0x400002e8 )          // DMA Target Address Register channel 14     
#define DCMD14     ( 0x400002eC )          // DMA Command Address Register channel 14     
#define DDADR15    ( 0x400002f0 )          // DMA Descriptor Address Register channel 15     
#define DSADR15    ( 0x400002f4 )          // DMA Source Address Register channel 15     
#define DTADR15    ( 0x400002f8 )          // DMA Target Address Register channel 15     
#define DCMD15     ( 0x400002fC )          // DMA Command Address Register channel 15     
//     Full Function UART        
#define FFRBR      ( 0x40100000 )          // Receive Buffer Register (read only)     
//#define FFRBR      ( 0x40200000 )
#define FFTHR      ( 0x40100000 )          // Transmit Holding Register (write only)    
//#define FFTHR      ( 0x40200000 ) 
#define FFIER      ( 0x40100004 )          // Interrupt Enable Register (read/write)
//#define FFIER      ( 0x40200004 )               
#define FFIIR      ( 0x40100008 )          // Interrupt ID Register (read only)     
//#define FFIIR      ( 0x40200008 )         
#define FFFCR      ( 0x40100008 )          // FIFO Control Register (write only)
//#define FFFCR      ( 0x40200008 )     
#define FFLCR      ( 0x4010000C )          // Line Control Register (read/write)  
//#define FFLCR      ( 0x4020000C )   
#define FFMCR      ( 0x40100010 )          // Modem Control Register (read/write)    
//#define FFMCR      ( 0x40200010 ) 
#define FFLSR      ( 0x40100014 )          // Line Status Register (read only)
//#define FFLSR      ( 0x40200014 )     
#define FFMSR      ( 0x40100018 )          // Modem Status Register (read only)
//#define FFMSR      ( 0x40200018 )     
#define FFSPR      ( 0x4010001C )          // Scratch Pad Register (read/write)
//#define FFSPR      ( 0x4020001C )      
#define FFDLL      ( 0x40100000 )          // baud divisor lower byte (read/write)  
//#define FFDLL      ( 0x40200000 )   
#define FFDLH      ( 0x40100004 )          // baud divisor higher byte (read/write)  
//#define FFDLH      ( 0x40200004 )   
#define FFISR      ( 0x40100020 )          // slow Infrared Select Register (read/write)   
//#define FFISR      ( 0x40200020 )  
//     Bluetooth UART        
#define BTRBR      ( 0x40200000 )          // Receive Buffer Register (read only)     
#define BTTHR      ( 0x40200000 )          // Transmit Holding Register (write only)     
#define BTIER      ( 0x40200004 )          // Interrupt Enable Register (read/write)
#define BTIIR      ( 0x40200008 )          // Interrupt ID Register (read only)
#define BTFCR      ( 0x40200008 )          // FIFO Control Register (write only)
#define BTLCR      ( 0x4020000C )          // Line Control Register (read/write)
#define BTMCR      ( 0x40200010 )          // Modem Control Register (read/write)
#define BTLSR      ( 0x40200014 )          // Line Status Register (read only)
#define BTMSR      ( 0x40200018 )          // Modem Status Register (read only)
#define BTSPR      ( 0x4020001C )          // Scratch Pad Register (read/write)
#define BTDLL      ( 0x40200000 )          // baud divisor lower byte (read/write)
#define BTDLH      ( 0x40200004 )          // baud divisor higher byte (read/write)
#define BTISR      ( 0x40200020 )          // slow Infrared Select Register (read/write)
//     Standard UART   
#define STRBR      ( 0x40700000 )          // Receive Buffer Register (read only)
#define STTHR      ( 0x40700000 )          // Transmit Holding Register (write only)
#define STIER      ( 0x40700004 )          // Interrupt Enable Register (read/write)
#define STIIR      ( 0x40700008 )          // Interrupt ID Register (read only)
#define STFCR      ( 0x40700008 )          // FIFO Control Register (write only)
#define STLCR      ( 0x4070000C )          // Line Control Register (read/write)
#define STMCR      ( 0x40700010 )          // Modem Control Register (read/write)
#define STLSR      ( 0x40700014 )          // Line Status Register (read only)
#define STMSR      ( 0x40700018 )          // Reserved
#define STSPR      ( 0x4070001C )          // Scratch Pad Register (read/write)
#define STDLL      ( 0x40700000 )          // baud divisor lower byte (read/write)
#define STDLH      ( 0x40700004 )          // baud divisor higher byte (read/write)
#define STISR      ( 0x40700020 )          // slow Infrared Select Register (read/write)
//     I2C   
#define IBMR       ( 0x40301680 )          // I2C Bus Monitor Register - IBMR
#define IDBR       ( 0x40301688 )          // I2C Data Buffer Register - IDBR
#define ICR        ( 0x40301690 )          // I2C Control Register - ICR
#define ISR        ( 0x40301698 )          // I2C Status Register - ISR
#define ISAR       ( 0x403016A0 )          // I2C Slave Address Register - ISAR
//#define ICCR       ( 0x403016A8 )          // I2C Clock Count Register - ICCR
//     I2S   
#define SACR0      ( 0x40400000 )          // Global Control Register
#define SACR1      ( 0x40400004 )          // Serial Audio I2S/MSB-Justified Control Register
// -     0x4040-0008 )          // Reserved
#define SASR0      ( 0x4040000C )          // Serial Audio I2S/MSB-Justified Interface and FIFO Status Register
// -     0x4040-0010 )          // Reserved
#define SAIMR      ( 0x40400014 )          // Serial Audio Interrupt Mask Register
#define SAICR      ( 0x40400018 )          // Serial Audio Interrupt Clear Register
//      0x4040-001C  
//     through   
// Reserved    0x4040-0058 -  
#define SAITR      ( 0x4040005C )          // Serial Audio Interrupt Test Register
#define SADIV      ( 0x40400060 )          // "Audio clock divider register. See section Section 12.3, 揝erial Audio Clocks and Sampling Frequencies