vectors.s

移植到WLIT项目的redboot源代码

        ldr     r1,.__exception_handlers
        ldr     r2,[r1,#0x00]    // reset vector intstruction
        str     r2,[r0,#0x00]
        ldr     r2,=warm_reset
        str     r2,[r0,#0x20]
        // Relocate [copy] data from ROM to RAM
        ldr     r3,.__rom_data_start
        ldr     r4,.__ram_data_start
        ldr     r5,.__ram_data_end
        cmp     r4,r5           // jump if no data to move
        beq     2f
        sub     r3,r3,#4        // loop adjustments
        sub     r4,r4,#4
1:      ldr     r0,[r3,#4]!     // copy info
        str     r0,[r4,#4]!
        cmp     r4,r5
        bne     1b
2:
#endif

        // initialize interrupt/exception environments
        ldr     sp,.__startup_stack
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE)
        msr     cpsr,r0
        ldr     sp,.__exception_stack
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
        msr     cpsr,r0
        ldr     sp,.__exception_stack

        // initialize CPSR (machine state register)
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0

        // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!!
        msr     spsr,r0

        // initialize stack
        ldr     sp,.__startup_stack

        // clear BSS
        ldr     r1,.__bss_start
        ldr     r2,.__bss_end
        mov     r0,#0
        cmp     r1,r2
        beq     2f
1:      str     r0,[r1],#4
        cmp     r1,r2
        bne     1b
2:

        // Run kernel + application in THUMB mode
        THUMB_MODE(r1,10)

        LED 3
        //DELAY_FOR 0xffff,r9
        //wit_led_22_on

        
        // Call platform specific hardware initialization
        bl      hal_hardware_init

#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        bl      initialize_stub

        // Now that stub is initialized, change vector. It is possible
        // to single-step through most of the init code, except the below.
        // Put a breakpoint at the call to cyg_hal_invoke_constructors to
        // pass over this bit (s-s depends on internal state in the stub).
#endif

#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) || \
    defined(CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS)
        mov     r0,#0           // move vectors
        ldr     r1,=__exception_handlers
        ldr     r2,[r1,#0x04]   // undefined instruction
        str     r2,[r0,#0x04]
        ldr     r2,[r1,#0x24]   
        str     r2,[r0,#0x24]
#endif

	// FIXME: The line with the thumb check is a hack, allowing
	// the farm to run test. Problem is that virtual vector table
	// API needs to be ARM/Thumb consistent. Will fix later.
#if !defined(__thumb__) || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
    || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
        .extern hal_ctrlc_isr_init
        bl      hal_ctrlc_isr_init
#endif
#endif
        LED 2
        //DELAY_FOR 0xffff,r9
        //wit_led_32_on
        
        // Run through static constructors
        bl      cyg_hal_invoke_constructors
        
        LED 1
        //DELAY_FOR 0xffff,r9
        //wit_led_22_on
        
        // This starts up the eCos kernel
        bl      cyg_start
_start_hang:
        b       _start_hang
        .code   32
        
        .global reset_platform
        .type   reset_platform,function
reset_platform:         
#ifdef CYGSEM_HAL_ROM_MONITOR
        // initialize CPSR (machine state register)
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
        b       warm_reset
#else
        mov     r0,#0
        mov     pc,r0           // Jump to reset vector        
#endif                   

init_done:
        .long   0xDEADB00B

//
// Exception handlers
// Assumption: get here from a Supervisor context [mode]
//
        .code   32
undefined_instruction:

        ldr     sp,.__undef_exception_stack     // get good stack
        stmfd   sp!,{r0,fp,ip,lr}               
        mrs     r0,spsr
        stmfd   sp!,{r0}
        mov     ip,sp                   // save SP which will vanish with
                                        //   mode switch
        mrs     r0,cpsr                 // switch to Supervisor Mode
        bic     r0,r0,#CPSR_MODE_BITS
        orr     r0,r0,#CPSR_SUPERVISOR_MODE
        msr     cpsr,r0                 // sp,lr are now old values
        mov     fp,sp
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        ldr     sp,.__GDB_stack
        cmp     fp,sp                   // already on GDB stack?
        bhi     10f     
        ldr     r0,.__GDB_stack_base            
        cmp     fp,r0
        bls     10f                     // no - switch to GDB stack
                                        //      (already in sp)
        mov     sp,fp                   // yes - no switch
10:
#endif
        sub     sp,sp,#ARMREG_SIZE      // make space for frame
        stmea   sp,{r0-r10,fp}          // save immediately visible registers
        ldmfd   ip,{r0-r4}              // saved registers
        // Adjust PC according to CPU mode
        tst     r0,#CPSR_THUMB_ENABLE
        subeq   r4,r4,#4                // PC at time of interrupt (ARM)
        subne   r4,r4,#2                // PC at time of interrupt (thumb)
        str     r0,[sp,#armreg_cpsr]    // CPSR at time of interrupt
        str     r1,[sp,#armreg_r0]      // saved R0
        str     r2,[sp,#armreg_fp]      // saved FP
        str     r3,[sp,#armreg_ip]      // saved IP
        str     r4,[sp,#armreg_pc]      // PC at time of interrupt
        str     lr,[sp,#armreg_lr]      // LR at time of interrupt
        add     r0,ip,#ARMREG_SIZE
        str     fp,[sp,#armreg_sp]      // SP at time of interrupt
#ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
        mov     r0,sp
        bl      cyg_hal_report_undefined_instruction
#endif
        mov     v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
        b       call_exception_handler

        .code   32
software_interrupt:

        sub     sp,sp,#ARMREG_SIZE+16   // make space for frame
        stmea   sp,{r0-r10,fp}          // save immediately visible registers
        mrs     r0,spsr
        // Adjust PC according to CPU mode
        tst     r0,#CPSR_THUMB_ENABLE
        subeq   r3,lr,#4                // PC at time of interrupt (ARM)
        subne   r3,lr,#2                // PC at time of interrupt (thumb)
        str     r0,[sp,#armreg_cpsr]    // CPSR at time of interrupt
        str     ip,[sp,#armreg_ip]      // saved IP
        str     r3,[sp,#armreg_pc]      // PC at time of interrupt
        str     lr,[sp,#armreg_lr]      // LR at time of interrupt
        add     r0,sp,#ARMREG_SIZE+16
        str     r0,[sp,#armreg_sp]      // SP at time of interrupt
#ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
        mov     r0,sp
        bl      cyg_hal_report_software_interrupt
#endif
        mov     v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT
        b       call_exception_handler

        .code   32
abort_prefetch:

        ldr     sp,.__undef_exception_stack     // get good stack
        sub     lr,lr,#4                // PC at time of interrupt
        stmfd   sp!,{r0,fp,ip,lr}               
        mrs     r0,spsr
        stmfd   sp!,{r0}
        mov     ip,sp                   // save SP which will vanish with
                                        //   mode switch
        mrs     r0,cpsr                 // switch to Supervisor Mode
        bic     r0,r0,#CPSR_MODE_BITS
        orr     r0,r0,#CPSR_SUPERVISOR_MODE
        msr     cpsr,r0                 // sp,lr are now old values
        mov     fp,sp
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        ldr     sp,.__GDB_stack
        cmp     fp,sp                   // already on GDB stack?
        bhi     10f     
        ldr     r0,.__GDB_stack_base            
        cmp     fp,r0
        bls     10f                     // no - switch to GDB stack
                                        //      (already in sp)
        mov     sp,fp                   // yes - no switch
10:
#endif
        sub     sp,sp,#ARMREG_SIZE      // make space for frame
        stmea   sp,{r0-r10,fp}          // save immediately visible registers
        ldmfd   ip,{r0-r4}              // saved registers
        str     r0,[sp,#armreg_cpsr]    // CPSR at time of interrupt
        str     r1,[sp,#armreg_r0]      // saved R0
        str     r2,[sp,#armreg_fp]      // saved FP
        str     r3,[sp,#armreg_ip]      // saved IP
        str     r4,[sp,#armreg_pc]      // PC at time of interrupt
        str     lr,[sp,#armreg_lr]      // LR at time of interrupt
        add     r0,ip,#ARMREG_SIZE
        str     fp,[sp,#armreg_sp]      // SP at time of interrupt
#ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
        mov     r0,sp
        bl      cyg_hal_report_abort_prefetch
#endif
        mov     v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS
        b       call_exception_handler

        .code   32
abort_data:

        ldr     sp,.__undef_exception_stack     // get good stack
        sub     lr,lr,#4                // PC at time of interrupt
        stmfd   sp!,{r0,fp,ip,lr}               
        mrs     r0,spsr
        stmfd   sp!,{r0}
        mov     ip,sp                   // save SP which will vanish with
                                        //   mode switch
        mrs     r0,cpsr                 // switch to Supervisor Mode
        bic     r0,r0,#CPSR_MODE_BITS
        orr     r0,r0,#CPSR_SUPERVISOR_MODE
        msr     cpsr,r0                 // sp,lr are now old values
        mov     fp,sp
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        ldr     sp,.__GDB_stack
        cmp     fp,sp                   // already on GDB stack?
        bhi     10f     
        ldr     r0,.__GDB_stack_base            
        cmp     fp,r0
        bls     10f                     // no - switch to GDB stack
                                        //      (already in sp)
        mov     sp,fp                   // yes - no switch
10:
#endif
        sub     sp,sp,#ARMREG_SIZE      // make space for frame
        stmea   sp,{r0-r10,fp}          // save immediately visible registers
        ldmfd   ip,{r0-r4}              // saved registers
        str     r0,[sp,#armreg_cpsr]    // CPSR at time of interrupt
        str     r1,[sp,#armreg_r0]      // saved R0
        str     r2,[sp,#armreg_fp]      // saved FP
        str     r3,[sp,#armreg_ip]      // saved IP
        str     r4,[sp,#armreg_pc]      // PC at time of interrupt
        str     lr,[sp,#armreg_lr]      // LR at time of interrupt
        add     r0,ip,#ARMREG_SIZE
        str     fp,[sp,#armreg_sp]      // SP at time of interrupt
#ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
        mov     r0,sp
        bl      cyg_hal_report_abort_data
#endif
        mov     v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS
        b       call_exception_handler

        
//
// Dispatch an exception handler.

        .code   32
call_exception_handler:
        str     v1,[sp,#armreg_vector]
        mov     r0,sp

        THUMB_MODE(r9,10)

        bl      exception_handler
#ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
        mov     r0,sp
        bl      cyg_hal_report_exception_handler_returned
#endif

        ARM_MODE(r1,10)

// Restore [interrupted] context
        mov     ip,sp                   // get stack pointer

        mrs     r0,cpsr                 // move back to IRQ mode
        orr     r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
        msr     cpsr,r0
        nop
        nop

        ldr     lr,[ip,#armreg_lr]
        ldr     sp,[sp,#armreg_sp]
                        
        bic     r0,r0,#CPSR_MODE_BITS
        orr     r0,r0,#CPSR_IRQ_MODE
        msr     cpsr,r0

        mov     sp,ip
        ldr     lr,[sp,#armreg_pc]
        ldr     r0,[sp,#armreg_cpsr]
        ldr     ip,[sp,#armreg_ip]
        msr     spsr,r0
        ldmfd   sp,{r0-r10,fp}

        movs    pc,lr                   // restore PC from LR, CPSR from SPSR

// Handle device interrupts
// This is slightly more complicated than the other exception handlers because
// it needs to interface with the kernel (if present).

        .code   32
FIQ:
        // We can get here from supervisor mode or from IRQ mode.
        mrs     r8,spsr                 // CPSR at time of interrupt
        and     r9,r8,#CPSR_MODE_BITS   // isolate pre-interrupt mode
        cmp	r9,#CPSR_IRQ_MODE
        bne	1f
        // If FIQ interrupted IRQ mode, just return with FIQ disabled.
        // The common interrupt handling takes care of the rest.
        orr	r8,r8,#CPSR_FIQ_DISABLE
        msr	spsr,r8
        subs	pc,lr,#4
    1:
        // If FIQ interrupted supervisor mode, switch to IRQ mode and
        // fall through to IRQ handler.
        ldr     sp,.__exception_stack   // get good stack to save lr and spsr
        stmdb   sp,{r8,lr}
        mov     r8,#CPSR_IRQ_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE
        msr     cpsr,r8			// switch to IRQ mode
        ldr     sp,.__exception_stack   // get regs saved in FIQ mode
        ldmdb	sp,{sp,lr}
        msr     spsr,sp

        // now it looks like we got an IRQ instead of an FIQ except that
        // FIQ is disabled so we don't recurse.

IRQ:
        // Note: I use this exception stack while saving the context because
        // the current SP does not seem to be always valid in this CPU mode.
        ldr     sp,.__exception_stack   // get good stack
        sub     lr,lr,#4                // PC at time of interrupt
        stmfd   sp!,{r0,fp,ip,lr}               
        mrs     r0,spsr
        stmfd   sp!,{r0}

handle_IRQ_or_FIQ:              
        mov     ip,sp                   // save SP which will vanish with
                                        //   mode switch
        mrs     r0,cpsr                 // switch to Supervisor Mode
        bic     r0,r0,#CPSR_MODE_BITS
        orr     r0,r0,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE
        msr     cpsr,r0                 // sp,lr are now old values
        mov     fp,sp                   // save old SP
        sub     sp,sp,#ARMREG_SIZE      // make space for frame
        stmea   sp,{r0-r10,fp}          // save immediately visible registers
        ldmfd   ip,{r0-r4}              // saved registers
        str     r0,[sp,#armreg_cpsr]    // CPSR at time of interrupt
        str     r1,[sp,#armreg_r0]      // saved R0
        str     r2,[sp,#armreg_fp]      // saved FP
        str     r3,[sp,#armreg_ip]      // saved IP
        str     r4,[sp,#armreg_pc]      // PC at time of interrupt
        str     lr,[sp,#armreg_lr]      // LR at time of interrupt
        str     fp,[sp,#armreg_sp]      // SP at time of interrupt
        mov     v6,sp                   // Save pointer to register frame

//      mov     r0,sp