mycount.vhd

来自「新买的书」· VHDL 代码 · 共 38 行

-- Author: Elliot Hill
--
-- Description: This file is the base counter module for the MVP
-- (Mobile VideoPhone) thesis project. It is used
-- to count up to a certain number and then reset
-- to zero.
library ieee;
use ieee.std_logic_1164.all;
entity counter is port
(clkin, reset: in BIT;
total: in INTEGER;
OE: out BIT);
end;
architecture counter_arch of counter is
begin
-- We want the process to update everytime there is
-- a change on the clock or hsync signals.
process (clkin, reset)
variable count : INTEGER := 0;
begin
if (reset = '0' and reset'STABLE) then
if (clkin = '1' and clkin'EVENT) then
-- If the clk triggers and hsync is not asserted,
-- then increment the count. Note that OE is only
-- asserted when the counter reaches the number
-- specified by total. After that, it is 0.
count := count + 1;
if count = total then
OE <= '1', '0' after 20 ns;
end if;
end if;
elsif (reset = '1' and reset'EVENT) then
-- The reset input is asserted, so we want to reset
-- the counter.
count := 0;
end if;
end process;
end counter_arch;