📄 sfr6n.h
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unsigned char da0_addr; /* D-A register 0 */
#define da0 da0_addr
unsigned char da1_addr; /* D-A register 1 */
#define da1 da1_addr
/*
unsigned int ta11_addr;
#define ta11 ta11_addr
unsigned int ta21_addr;
#define ta21 ta21_addr
unsigned int ta41_addr;
#define ta41 ta41_addr
*/
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Processor mode register 0 bit
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit*/
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
#define pm06 pm0_addr.bit.b6 /* Port P40~P43 function select bit */
#define pm07 pm0_addr.bit.b7 /* BCLK output disable bit */
/*------------------------------------------------------
Processor mode register 1 bit
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm13 pm1_addr.bit.b3 /* Intermal reserved area expansion bit (62) */
#define pm14 pm1_addr.bit.b4 /* Memory area expansion bit (62) */
#define pm15 pm1_addr.bit.b5 /* (62) */
#define pm16 pm1_addr.bit.b6 /* Reserved bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit */
/*------------------------------------------------------
Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define csr csr_addr.byte
#define cs0 csr_addr.bit.b0 /* CS0 output enable bit */
#define cs1 csr_addr.bit.b1 /* CS1 output enable bit */
#define cs2 csr_addr.bit.b2 /* CS2 output enable bit */
#define cs3 csr_addr.bit.b3 /* CS3 output enable bit */
#define cs0w csr_addr.bit.b4 /* CS0 wait bit */
#define cs1w csr_addr.bit.b5 /* CS1 wait bit */
#define cs2w csr_addr.bit.b6 /* CS2 wait bit */
#define cs3w csr_addr.bit.b7 /* CS3 wait bit */
/*------------------------------------------------------
Addrese match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Addrese match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Addrese match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control register 0,1 */
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode register 0,1 */
#define prc2 prcr_addr.bit.b2 /* Enables writing to port P9 direction register */
/*------------------------------------------------------
Data bank register (62)
------------------------------------------------------*/
/*union byte_def dbr_addr;
#define dbr dbr_addr.byte
*/
//#define ofs dbr_addr.bit.b2 /* Offset bit */
//#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
//#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
//#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define crcin crcin_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc5 wdc_addr.bit.b5
#define wdc6 wdc_addr.bit.b6
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define tabsr tabsr_addr.byte
#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */
#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */
#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */
#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */
#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */
#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */
#define tb1s tabsr_addr.bit.b6 /* Timer B1 count start flag */
#define tb2s tabsr_addr.bit.b7 /* Timer B2 count start flag */
/*------------------------------------------------------
Timer B3,4,5 Count start flag (62)
------------------------------------------------------*/
union byte_def tbsr_addr;
#define tbsr tbsr_addr.byte
#define tb3s tbsr_addr.bit.b5 /* Timer B3 count start flag */
#define tb4s tbsr_addr.bit.b6 /* Timer B4 count start flag */
#define tb5s tbsr_addr.bit.b7 /* Timer B5 count start flag */
/*------------------------------------------------------
Three-phase PWM control regester 0 (62)
------------------------------------------------------*/
union byte_def invc0_addr;
#define invc0 invc0_addr.byte
#define inv00 invc0_addr.bit.b0 /* (62) */
#define inv01 invc0_addr.bit.b1 /* (62) */
#define inv02 invc0_addr.bit.b2 /* (62) */
#define inv03 invc0_addr.bit.b3 /* (62) */
#define inv04 invc0_addr.bit.b4 /* (62) */
#define inv05 invc0_addr.bit.b5 /* (62) */
#define inv06 invc0_addr.bit.b6 /* (62) */
#define inv07 invc0_addr.bit.b7 /* (62) */
/*------------------------------------------------------
Three-phase PWM control regester 1 (62)
------------------------------------------------------*/
union byte_def invc1_addr;
#define invc1 invc1_addr.byte
#define inv10 invc1_addr.bit.b0 /* (62) */
#define inv11 invc1_addr.bit.b1 /* (62) */
#define inv12 invc1_addr.bit.b2 /* (62) */
#define inv14 invc1_addr.bit.b4 /* Reserved bit */
/*------------------------------------------------------
Three-phase output buffer register 0 (62)
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* (62) */
#define dub0 idb0_addr.bit.b1 /* (62) */
#define dv0 idb0_addr.bit.b2 /* (62) */
#define dvb0 idb0_addr.bit.b3 /* (62) */
#define dw0 idb0_addr.bit.b4 /* (62) */
#define dwb0 idb0_addr.bit.b5 /* (62) */
/*------------------------------------------------------
Three-phase output buffer register 1 (62)
------------------------------------------------------*/
union byte_def idb1_addr;
#define idb1 idb1_addr.byte
#define du1 idb1_addr.bit.b0 /* (62) */
#define dub1 idb1_addr.bit.b1 /* (62) */
#define dv1 idb1_addr.bit.b2 /* (62) */
#define dvb1 idb1_addr.bit.b3 /* (62) */
#define dw1 idb1_addr.bit.b4 /* (62) */
#define dwb1 idb1_addr.bit.b5 /* (62) */
/*------------------------------------------------------
(62)
------------------------------------------------------*/
union byte_def dtt_addr;
#define dtt dtt_addr.byte
/*------------------------------------------------------
(62)
------------------------------------------------------*/
union byte_def ictb2_addr;
#define ictb2 ictb2_addr.byte
/*------------------------------------------------------
One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define onsf onsf_addr.byte
#define ta0os onsf_addr.bit.b0 /* Timer A0 one-shot start flag */
#define ta1os onsf_addr.bit.b1 /* Timer A1 one-shot start flag */
#define ta2os onsf_addr.bit.b2 /* Timer A2 one-shot start flag */
#define ta3os onsf_addr.bit.b3 /* Timer A3 one-shot start flag */
#define ta4os onsf_addr.bit.b4 /* Timer A4 one-shot start flag */
#define ta0tgl onsf_addr.bit.b6 /* Timer A0 event/trigger select bit */
#define ta0tgh onsf_addr.bit.b7 /* Timer A0 event/trigger select bit */
/*------------------------------------------------------
Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define cpsrf cpsrf_addr.byte
#define cpsr cpsrf_addr.bit.b7 /* Clock prescaler reset flag */
/*------------------------------------------------------
Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define trgsr trgsr_addr.byte
#define ta1tgl trgsr_addr.bit.b0 /* Timer A1 event/trigger select bit */
#define ta1tgh trgsr_addr.bit.b1 /* Timer A1 event/trigger select bit */
#define ta2tgl trgsr_addr.bit.b2 /* Timer A2 event/trigger select bit */
#define ta2tgh trgsr_addr.bit.b3 /* Timer A2 event/trigger select bit */
#define ta3tgl trgsr_addr.bit.b4 /* Timer A3 event/trigger select bit */
#define ta3tgh trgsr_addr.bit.b5 /* Timer A3 event/trigger select bit */
#define ta4tgl trgsr_addr.bit.b6 /* Timer A4 event/trigger select bit */
#define ta4tgh trgsr_addr.bit.b7 /* Timer A4 event/trigger select bit */
/*------------------------------------------------------
Up/down flag
------------------------------------------------------*/
union byte_def udf_addr;
#define udf udf_addr.byte
#define ta0ud udf_addr.bit.b0 /* Timer A0 up/down flag */
#define ta1ud udf_addr.bit.b1 /* Timer A1 up/down flag */
#define ta2ud udf_addr.bit.b2 /* Timer A2 up/down flag */
#define ta3ud udf_addr.bit.b3 /* Timer A3 up/down flag */
#define ta4ud udf_addr.bit.b4 /* Timer A4 up/down flag */
#define ta2p udf_addr.bit.b5 /* Timer A2 two-phase pulse signal processing select bit */
#define ta3p udf_addr.bit.b6 /* Timer A3 two-phase pulse signal processing select bit */
#define ta4p udf_addr.bit.b7 /* Timer A4 two-phase pulse signal processing select bit */
/*------------------------------------------------------
UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define ucon ucon_addr.byte
#define u0irs ucon_addr.bit.b0 /* UART0 transmit interrupt cause select bit */
#define u1irs ucon_addr.bit.b1 /* UART1 transmit interrupt cause select bit */
#define u0rrm ucon_addr.bit.b2 /* UART0 continuous receive mode enable bit */
#define u1rrm ucon_addr.bit.b3 /* UART1 continuous receive mode enable bit */
#define clkmd0 ucon_addr.bit.b4 /* CLK/CLKS select bit 0 */
#define clkmd1 ucon_addr.bit.b5 /* CLK/CLKS select bit 1 */
#define rcsp ucon_addr.bit.b6 /* Separate CTS/RTS bit */
/*------------------------------------------------------
UART2 transmit/receive control register 1 (61)
------------------------------------------------------*/
union byte_def u2c1_addr;
#define u2c1 u2c1_addr.byte
#define te_u2c1 u2c1_addr.bit.b0 /* Transmit enable bit */
#define ti_u2c1 u2c1_addr.bit.b1 /* Transmit buffer empty flag */
#define re_u2c1 u2c1_addr.bit.b2 /* Receive enable bit */
#define ri_u2c1 u2c1_addr.bit.b3 /* Receive complete flag */
#define u2irs u2c1_addr.bit.b4 /* UART2 transmit interrupt cause select bit */
#define u2rrm u2c1_addr.bit.b5 /* UART2 continuous receive mode enable bit */
#define u2lch u2c1_addr.bit.b6 /* Data logic select bit */
#define u2ere u2c1_addr.bit.b7 /* Error signal output enable bit */
/*------------------------------------------------------
UART2 special mode register2 (62)
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define u2smr2 u2smr2_addr.byte
#define iicm2 u2smr2_addr.bit.b0 /* IIC mode selection bit 2*/
#define csc u2smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc u2smr2_addr.bit.b2 /* SCL wait output bit */
#define als u2smr2_addr.bit.b3 /* SDA output stop bit */
#define stac u2smr2_addr.bit.b4 /* UART2 initialization bit */
#define swc2 u2smr2_addr.bit.b5 /* SCL wait output bit 2 */
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