📄 gyromousev1_2.lst
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(0219) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
0078: 4F MOV X,SP
0079: 5B MOV A,X
007A: 01 03 ADD A,3
007C: 53 F9 MOV [249],A
007E: 55 F8 3A MOV [248],58
0081: 50 06 MOV A,6
0083: 00 SWI
0084: 71 10 OR F,16
0086: 51 F9 MOV A,[249]
0088: 60 E8 MOV REG[232],A
008A: 51 F8 MOV A,[248]
008C: 60 EA MOV REG[234],A
008E: 70 EF AND F,239
(0220) ENDIF ;(SUPPLY_VOLTAGE)
(0221)
(0222) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
0090: 55 F8 00 MOV [248],0
(0223) mov [bSSC_KEYSP], 0
0093: 55 F9 00 MOV [249],0
(0224)
(0225) ;---------------------------------------
(0226) ; Initialize Crystal Oscillator and PLL
(0227) ;---------------------------------------
(0228)
(0229) IF ( SELECT_32K & WAIT_FOR_32K )
(0230) ; If the user has requested the External Crystal Oscillator (ECO) then turn it
(0231) ; on and wait for it to stabilize and the system to switch over to it. The PLL
(0232) ; is left off. Set the SleepTimer period is set to 1 sec to time the wait for
(0233) ; the ECO to stabilize.
(0234) ;
(0235) M8C_SetBank1
(0236) mov reg[OSC_CR0], (SELECT_32K_JUST | OSC_CR0_SLEEP_1Hz | OSC_CR0_CPU_12MHz)
(0237) M8C_SetBank0
(0238) M8C_ClearWDTAndSleep ; Reset the sleep timer to get a full second
(0239) or reg[INT_MSK0], INT_MSK0_SLEEP ; Enable latching of SleepTimer interrupt
(0240) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0241) .WaitFor1s:
(0242) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0243) jz .WaitFor1s ; Interrupt will latch but will not dispatch
(0244) ; since interrupts are not globally enabled
(0245) ELSE ; !( SELECT_32K & WAIT_FOR_32K )
(0246) ; Either no ECO, or waiting for stable clock is to be done in main
(0247) M8C_SetBank1
0096: 71 10 OR F,16
(0248) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
0098: 62 E0 02 MOV REG[224],2
(0249) M8C_SetBank0
009B: 70 EF AND F,239
(0250) M8C_ClearWDTAndSleep ; Reset the watch dog
009D: 62 E3 38 MOV REG[227],56
(0251)
(0252) ENDIF ;( SELECT_32K & WAIT_FOR_32K )
(0253)
(0254) IF ( PLL_MODE )
(0255) ; Crystal is now fully operational (assuming WAIT_FOR_32K was enabled).
(0256) ; Now start up PLL if selected, and wait 16 msec for it to stabilize.
(0257) ;
(0258) M8C_SetBank1
(0259) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
(0260) M8C_SetBank0
(0261) M8C_ClearWDTAndSleep ; Reset the sleep timer to get full period
(0262) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0263)
(0264) .WaitFor16ms:
(0265) tst reg[INT_CLR0],INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0266) jz .WaitFor16ms
(0267) M8C_SetBank1 ; continue boot at CPU Speed of SYSCLK/2
(0268) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_12MHz)
(0269) M8C_SetBank0
(0270)
(0271) IF ( WAIT_FOR_32K )
(0272) ELSE ; !( WAIT_FOR_32K )
(0273) ; Option settings (PLL-Yes, ECO-No) are incompatible - force a syntax error
(0274) ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
(0275) ENDIF ;(WAIT_FOR_32K)
(0276) ENDIF ;(PLL_MODE)
(0277)
(0278) ;------------------------
(0279) ; Close CT leakage path.
(0280) ;------------------------
(0281) mov reg[ACB00CR0], 05h
00A0: 62 71 05 MOV REG[113],5
(0282) mov reg[ACB01CR0], 05h
00A3: 62 75 05 MOV REG[117],5
(0283) mov reg[ACB02CR0], 05h
00A6: 62 79 05 MOV REG[121],5
(0284) mov reg[ACB03CR0], 05h
00A9: 62 7D 05 MOV REG[125],5
(0285)
(0286) ;-------------------------
(0287) ; Load Base Configuration
(0288) ;-------------------------
(0289) ; Load global parameter settings and load the user modules in the
(0290) ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
(0291) ; to minimize start up time; (2) We may still need to play with the
(0292) ; Sleep Timer.
(0293) ;
(0294) lcall LoadConfigInit
00AC: 7C 03 47 LCALL 0x0347
(0295)
(0296) ;-----------------------------------
(0297) ; Initialize C Run-Time Environment
(0298) ;-----------------------------------
(0299) IF ( C_LANGUAGE_SUPPORT )
(0300) mov A,0 ; clear the 'bss' segment to zero
00AF: 50 00 MOV A,0
(0301) mov [__r0],<__bss_start
00B1: 55 82 8D MOV [__r0],141
(0302) BssLoop:
(0303) cmp [__r0],<__bss_end
00B4: 3C 82 9F CMP [130],159
(0304) jz BssDone
00B7: A0 05 JZ 0x00BD
(0305) mvi [__r0],A
00B9: 3F 82 MVI [__r0],A
(0306) jmp BssLoop
00BB: 8F F8 JMP 0x00B4
(0307) BssDone:
(0308) mov A,>__idata_start ; copy idata to data segment
00BD: 50 01 MOV A,1
(0309) mov X,<__idata_start
00BF: 57 50 MOV X,80
(0310) mov [__r0],<__data_start
00C1: 55 82 00 MOV [__r0],0
(0311) IDataLoop:
(0312) cmp [__r0],<__data_end
00C4: 3C 82 76 CMP [130],118
(0313) jz C_RTE_Done
00C7: A0 0B JZ 0x00D3
(0314) push A
00C9: 08 PUSH A
(0315) romx
00CA: 28 ROMX
(0316) mvi [__r0],A
00CB: 3F 82 MVI [__r0],A
(0317) pop A
00CD: 18 POP A
(0318) inc X
00CE: 75 INC X
(0319) adc A,0
00CF: 09 00 ADC A,0
(0320) jmp IDataLoop
00D1: 8F F2 JMP 0x00C4
(0321)
(0322) C_RTE_Done:
(0323)
(0324) ENDIF ; C_LANGUAGE_SUPPORT
(0325)
(0326) ;-------------------------------
(0327) ; Voltage Stabilization for SMP
(0328) ;-------------------------------
(0329)
(0330) IF ( SUPPLY_VOLTAGE ) ; 1 Means 5 Volts
(0331) IF ( SWITCH_MODE_PUMP ^ 1 ) ; SMP is operational
(0332) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0333) ; When using the SMP at 5V, we must wait for Vdd to slew from 3.1V to
(0334) ; 5V before enabling the Precision Power-On Reset (PPOR).
(0335) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0336) or reg[INT_MSK0],INT_MSK0_SLEEP
(0337) M8C_SetBank1
(0338) and reg[OSC_CR0], ~OSC_CR0_SLEEP
(0339) or reg[OSC_CR0], OSC_CR0_SLEEP_512Hz
(0340) M8C_SetBank0
(0341) M8C_ClearWDTAndSleep ; Restart the sleep timer
(0342) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0343) .WaitFor2ms:
(0344) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0345) jz .WaitFor2ms ; Branch fails when 2 msec has passed
(0346) ENDIF ; ( SWITCH_MODE_PUMP ^ 1 )
(0347) ENDIF ; ( SUPPLY_VOLTAGE )
(0348)
(0349) ;-------------------------------
(0350) ; Set Power-On Reset (POR) Level
(0351) ;-------------------------------
(0352) M8C_SetBank1
00D3: 71 10 OR F,16
(0353)
(0354) IF ( SUPPLY_VOLTAGE ) ; 1 Means 5 Volts
(0355) IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ; Also 24MHz?
(0356) ; no, set 4.5V POR in user code, if desired
(0357) ELSE ; 24HMz ;
(0358) or reg[VLT_CR], VLT_CR_POR_HIGH ; yes, highest POR trip point required
(0359) ENDIF ; OSC_CRO_CPU_24MHz
(0360) ENDIF ; 5V
(0361)
(0362) M8C_SetBank0
00D5: 70 EF AND F,239
(0363)
(0364) ;----------------------------
(0365) ; Wrap up and invoke "main"
(0366) ;----------------------------
(0367)
(0368) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0369) ; no interrupts should be enabled now, so may as well clear the register.
(0370) ;
(0371) mov reg[INT_MSK0],0
00D7: 62 E0 00 MOV REG[224],0
(0372)
(0373) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0374) ;
(0375) M8C_SetBank1
00DA: 71 10 OR F,16
(0376) mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
00DC: 62 E0 02 MOV REG[224],2
(0377) M8C_SetBank0
00DF: 70 EF AND F,239
(0378)
(0379) ; Global Interrupt are NOT enabled, this should be done in main().
(0380) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0381) ; Global Interrupts should be enabled as soon as possible in main().
(0382) ;
(0383) mov reg[INT_VC],0 ; Clear any pending interrupts which may
00E1: 62 E2 00 MOV REG[226],0
(0384) ; have been set during the boot process.
(0385) IF ENABLE_LJMP_TO_MAIN
(0386) ljmp _main ; goto main (no return)
(0387) ELSE
(0388) lcall _main ; call main
00E4: 7C 06 8C LCALL __text_start
(0389) .Exit:
(0390) jmp .Exit ; Wait here after return till power-off or reset
00E7: 8F FF JMP 0x00E7
(0391) ENDIF
(0392)
(0393) ;---------------------------------
(0394) ; Library Access to Global Parms
(0395) ;---------------------------------
(0396) ;
(0397) bGetPowerSetting:
(0398) _bGetPowerSetting:
(0399) ; Synthesize the "power setting" value used by chips with SlowIMO mode.
(0400) ; Returns value of POWER_SETTING in the A register.
(0401) ; No inputs. No Side Effects.
(0402) ;
(0403) IF ( SUPPLY_VOLTAGE ) ; 1 means 5.0V
(0404) mov A, POWER_SET_5V0_24MHZ ; Supply & Internal Main Oscillator speed
(0405) ELSE
(0406) mov A, POWER_SET_3V3_24MHZ ; Supply & Internal Main Oscillator speed
00E9: 50 08 MOV A,8
(0407) ENDIF
(0408) ret
00EB: 7F RET
00EC: 30 HALT
00ED: 30 HALT
00EE: 30 HALT
00EF: 30 HALT
00F0: 30 HALT
00F1: 30 HALT
00F2: 30 HALT
00F3: 30 HALT
00F4: 30 HALT
00F5: 30 HALT
00F6: 30 HALT
00F7: 30 HALT
00F8: 30 HALT
00F9: 30 HALT
00FA: 30 HALT
00FB: 30 HALT
00FC: 30 HALT
00FD: 30 HALT
00FE: 30 HALT
00FF: 30 HALT
0100: 30 HALT
0101: 30 HALT
0102: 30 HALT
0103: 30 HALT
0104: 30 HALT
0105: 30 HALT
0106: 30 HALT
0107: 30 HALT
0108: 30 HALT
0109: 30 HALT
010A: 30 HALT
010B: 30 HALT
010C: 30 HALT
010D: 30 HALT
010E: 30 HALT
010F: 30 HALT
0110: 30 HALT
0111: 30 HALT
0112: 30 HALT
0113: 30 HALT
0114: 30 HALT
0115: 30 HALT
0116: 30 HALT
0117: 30 HALT
0118: 30 HALT
0119: 30 HALT
011A: 30 HALT
011B: 30 HALT
011C: 30 HALT
011D: 30 HALT
011E: 30 HALT
011F: 30 HALT
0120: 30 HALT
0121: 30 HALT
0122: 30 HALT
0123: 30 HALT
0124: 30 HALT
0125: 30 HALT
0126: 30 HALT
0127: 30 HALT
0128: 30 HALT
0129: 30 HALT
012A: 30 HALT
012B: 30 HALT
012C: 30 HALT
012D: 30 HALT
012E: 30 HALT
012F: 30 HALT
0130: 30 HALT
0131: 30 HALT
0132: 30 HALT
0133: 30 HALT
0134: 30 HALT
0135: 30 HALT
0136: 30 HALT
0137: 30 HALT
0138: 30 HALT
0139: 30 HALT
013A: 30 HALT
013B: 30 HALT
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