📄 uart_1int.lis
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0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000 VLT_CR_3V0_POR: equ 00h ; -- deprecated symbols --
0010 VLT_CR_4V5_POR: equ 10h ; deprecated
0020 VLT_CR_4V75_POR: equ 20h ; deprecated
0030 VLT_CR_DISABLE: equ 30h ; deprecated
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export _UART_1_TX_ISR
export _UART_1_RX_ISR
IF (UART_1_RXBUF_ENABLE)
export UART_1_aRxBuffer
export _UART_1_aRxBuffer
export UART_1_bRxCnt
export _UART_1_bRxCnt
export UART_1_fStatus
export _UART_1_fStatus
ENDIF
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
AREA InterruptRAM (RAM, REL, CON)
IF (UART_1_RXBUF_ENABLE)
0000 UART_1_fStatus:
0000 _UART_1_fStatus: BLK 1
0001 UART_1_bRxCnt:
0001 _UART_1_bRxCnt: BLK 1
AREA UART_1_RAM (RAM, REL, CON)
0000 UART_1_aRxBuffer:
0000 _UART_1_aRxBuffer: BLK UART_1_RX_BUFFER_SIZE
ENDIF
AREA InterruptRAM (RAM, REL, CON)
;@PSoC_UserCode_INIT@ (Do not change this line.)
;---------------------------------------------------
; Insert your custom declarations below this banner
;---------------------------------------------------
;------------------------
; Includes
;------------------------
;------------------------
; Constant Definitions
;------------------------
;------------------------
; Variable Allocation
;------------------------
;---------------------------------------------------
; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
AREA UserModules (ROM, REL, CON)
;-----------------------------------------------------------------------------
; FUNCTION NAME: _UART_1_TX_ISR
;
; DESCRIPTION:
; UART TX interrupt handler for instance UART_1.
;
; This is a place holder function. If the user requires use of an interrupt
; handler for this function, then place code where specified.
;-----------------------------------------------------------------------------
0000 _UART_1_TX_ISR:
0000 ;@PSoC_UserCode_BODY_1@ (Do not change this line.)
0000 ;---------------------------------------------------
0000 ; Insert your custom code below this banner
0000 ;---------------------------------------------------
0000 ; NOTE: interrupt service routines must preserve
0000 ; the values of the A and X CPU registers.
0000
0000 ;---------------------------------------------------
0000 ; Insert your custom code above this banner
0000 ;---------------------------------------------------
0000 ;@PSoC_UserCode_END@ (Do not change this line.)
0000 7E reti
0001
0001
0001 ;-----------------------------------------------------------------------------
0001 ; FUNCTION NAME: _UART_1_RX_ISR
0001 ;
0001 ; DESCRIPTION:
0001 ; UART RX interrupt handler for instance UART_1.
0001 ; This ISR handles the background processing of received characters if
0001 ; the buffer is enabled.
0001 ;
0001 ;
0001 ; The following assumes that the RX buffer feature has been enabled.
0001 ;
0001 ; SIDE EFFECTS:
0001 ; There are 3 posible errors that may occur with the serial port.
0001 ; 1) Parity Error
0001 ; 2) Framing Error
0001 ; 3) OverRun Error
0001 ;
0001 ; This user module check for parity and framing error. If either of these
0001 ; two errors are detected, the data is read and ignored. When an overRun
0001 ; error occur⌨️ 快捷键说明
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