📄 uart_1int.lis
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0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; FILENAME: UART_1INT.asm
0000 ;; Version: 5.2, Updated on 2005/09/30 at 16:26:37
0000 ;; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
0000 ;;
0000 ;; DESCRIPTION: UART Interrupt Service Routine.
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0000
0004 UART_1_TX_INT_MASK: equ 04h
00E1 UART_1_TX_INT_REG: equ 0e1h ;TX interrupt address
0008 UART_1_RX_INT_MASK: equ 08h ;mask value for global int reg bit for RX instance
00E1 UART_1_RX_INT_REG: equ 0e1h ;RX interrupt address
0000
0001 UART_1_RXBUF_ENABLE: equ 1
0000
0000 ; Interrupt control masks
0001 UART_1_ENABLE_RX_INT: equ 0x01
0000 UART_1_DISABLE_RX_INT: equ 0x00
0002 UART_1_ENABLE_TX_INT: equ 0x02
0000 UART_1_DISABLE_TX_INT: equ 0x00
0000
0000 UART_1_INT_MODE_TX_REG_EMPTY: equ 0x00
0001 UART_1_INT_MODE_TX_COMPLETE: equ 0x01
0000
0000 UART_1_RX_IGNORE_BELOW: equ 0h
0010 UART_1_RX_BUFFER_SIZE: equ 10h
000D UART_1_CMD_TERM: equ dh
0020 UART_1_DELIMITER: equ 20h
0000
0000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0000 ; WARNING WARNING WARNING
0000 ; The following equates are for backwards
0000 ; compatibility only and should not be used
0000 ; for new designs.
0000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0000
0000 ;------------------------------------
0000 ; Parity masks
0000 ;------------------------------------
0000 UART_PARITY_NONE: equ 00h
0002 UART_PARITY_EVEN: equ 02h
0006 UART_PARITY_ODD: equ 06h
0000
0000 ;------------------------------------
0000 ; TX Status Register masks
0000 ;------------------------------------
0020 UART_TX_COMPLETE: equ 20h
0010 UART_TX_BUFFER_EMPTY: equ 10h
0000
0000 ;------------------------------------
0000 ; RX Status Register masks
0000 ;------------------------------------
0010 UART_RX_ACTIVE: equ 10h
0008 UART_RX_COMPLETE: equ 08h
0080 UART_RX_PARITY_ERROR: equ 80h
0040 UART_RX_OVERRUN_ERROR: equ 40h
0020 UART_RX_FRAMING_ERROR: equ 20h
00E0 UART_RX_NO_ERROR: equ E0h
0000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0000 ; END WARNING
0000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0000
0000
0000
0000 ;------------------------------------
0000 ; Parity masks
0000 ;------------------------------------
0000 UART_1_PARITY_NONE: equ 00h
0002 UART_1_PARITY_EVEN: equ 02h
0006 UART_1_PARITY_ODD: equ 06h
0000
0000 ;------------------------------------
0000 ; TX Status Register masks
0000 ;------------------------------------
0020 UART_1_TX_COMPLETE: equ 20h
0010 UART_1_TX_BUFFER_EMPTY: equ 10h
0000
0000 ;------------------------------------
0000 ; RX Status Register masks
0000 ;------------------------------------
0010 UART_1_RX_ACTIVE: equ 10h
0008 UART_1_RX_COMPLETE: equ 08h
0008 UART_1_RX_REG_FULL: equ 08h
0080 UART_1_RX_PARITY_ERROR: equ 80h
0040 UART_1_RX_OVERRUN_ERROR: equ 40h
0020 UART_1_RX_FRAMING_ERROR: equ 20h
00E0 UART_1_RX_ERROR: equ E0h
0001 UART_1_RX_ENABLE: equ 01h
0000
00F0 UART_1_RX_BUF_ERROR: equ F0h ; Mask for any Rx that may occur.
0010 UART_1_RX_BUF_OVERRUN: equ 10h ; This indicates the software buffer has
0000 ; been over run.
0001 UART_1_RX_BUF_CMDTERM: equ 01h ; Command terminator has been received.
0000
0001 UART_1_RX_NO_DATA: equ 01h
00E0 UART_1_RX_NO_ERROR: equ E0h
0000
0000
0000 ;--------------------------------------------------
0000 ; Registers Address Constants for UART_1
0000 ;--------------------------------------------------
0000 ;---------------------------------
0000 ; Registers used by TX
0000 ;---------------------------------
002B UART_1_TX_CONTROL_REG: equ 2bh ; Control register
0028 UART_1_TX_SHIFT_REG: equ 28h ; TX Shift Register register
0029 UART_1_TX_BUFFER_REG: equ 29h ; TX Buffer Register
0028 UART_1_TX_FUNC_REG: equ 28h ; Function register
0029 UART_1_TX_INPUT_REG: equ 29h ; Input register
002A UART_1_TX_OUTPUT_REG: equ 2ah ; Output register
0000
0000 ;---------------------------------
0000 ; Registers used by RX
0000 ;---------------------------------
002F UART_1_RX_CONTROL_REG: equ 2fh ; Control register
002C UART_1_RX_SHIFT_REG: equ 2ch ; RX Shift Register register
002E UART_1_RX_BUFFER_REG: equ 2eh ; RX Buffer Register
002C UART_1_RX_FUNC_REG: equ 2ch ; Function register
002D UART_1_RX_INPUT_REG: equ 2dh ; Input register
002E UART_1_RX_OUTPUT_REG: equ 2eh ; Output register
0000
0000 ; end of file UART_1.inc
0000 SYSTEM_STACK_PAGE: equ 0
0000 SYSTEM_STACK_BASE_ADDR: equ 0h
0000 SYSTEM_LARGE_MEMORY_MODEL: equ 0
0001 SYSTEM_SMALL_MEMORY_MODEL: equ 1
0001 SYSTEM_TOOLS: equ 1
0001 SYSTEM_IDXPG_TRACKS_STK_PP: equ 1
0000 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 0
0000 SYSTEM_MULTIPAGE_STACK: equ 0
0000
0000
0000 ; ******* Function Class Definitions *******
0000 ;
0000 ; These definitions are used to describe RAM access patterns. They provide
0000 ; documentation and they control prologue and epilogue macros that perform
0000 ; the necessary housekeeping functions for large memory model devices like
0000 ; the CY8C27x66 and CY8C29x66.
0000
0001 RAM_USE_CLASS_1: equ 1 ; PUSH, POP & I/O access
0002 RAM_USE_CLASS_2: equ 2 ; Indexed address mode on stack page
0004 RAM_USE_CLASS_3: equ 4 ; Indexed address mode to any page
0008 RAM_USE_CLASS_4: equ 8 ; Direct/Indirect address mode access
0000
0000
0000 ; ******* Page Pointer Manipulation Macros *******
0000 ;
0000 ; Most of the following macros are conditionally compiled so they only
0000 ; produce code if the large memory model is selected.
0000
0000 ;-----------------------------------------------
0000 ; Set Stack Page Macro
0000 ;-----------------------------------------------
0000 ;
0000 ; DESC: Modify STK_PP in the large or small memory Models.
0000 ;
0000 ; INPUT: Constant (e.g., SYSTEM_STACK_PAGE) that specifies the RAM page on
0000 ; which stack operations like PUSH and POP store and retrieve their
0000 ; data
0000 ;
0000 ; COST: 8 instruction cycles (in LMM only)
0000
0000 macro RAM_SETPAGE_STK( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[STK_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_CUR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[CUR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[IDX_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVW( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVW_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX2STK
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_MULTIPAGE_STACK )
0000 mov A, reg[STK_PP]
0000 mov reg[IDX_PP], A
0000 ELSE
0000 RAM_SETPAGE_IDX SYSTEM_STACK_PAGE
0000 ENDIF
0000 ENDIF
0000 macro RAM_CHANGE_PAGE_MODE( MODE )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
0000 or F, FLAG_PGMODE_MASK & @MODE
0000 ENDIF
0000 macro RAM_SET_NATIVE_PAGING
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
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