e100_557.h

ddk开发pci范例,使用9054芯片

/****************************************************************************
** COPYRIGHT (C) 1994-1997 INTEL CORPORATION                               **
** DEVELOPED FOR MICROSOFT BY INTEL CORP., HILLSBORO, OREGON               **
** HTTP://WWW.INTEL.COM/                                                   **
** THIS FILE IS PART OF THE INTEL ETHEREXPRESS PRO/100B(TM) AND            **
** ETHEREXPRESS PRO/100+(TM) NDIS 5.0 MINIPORT SAMPLE DRIVER               **
****************************************************************************/

/****************************************************************************
Module Name:
    e100_557.h  (82557.h)

This driver runs on the following hardware:
    - 82558 based PCI 10/100Mb ethernet adapters
    (aka Intel EtherExpress(TM) PRO Adapters)

Environment:
    Kernel Mode - Or whatever is the equivalent on WinNT

Revision History
    - JCB 8/14/97 Example Driver Created
    - Dchen 11-01-99    Modified for the new sample driver
*****************************************************************************/

#ifndef _E100_557_H
#define _E100_557_H

//-------------------------------------------------------------------------
// D100 Stepping Defines
//-------------------------------------------------------------------------
#define D100_A_STEP                 0   // NEVER SHIPPED
#define D100_B_STEP                 1   // d100 first shipped silicon
#define D100_C_STEP                 2   // d100' (c-step) with vendor/id and hw fix
#define D101_A_STEP                 4   // first silicon of d101

//-------------------------------------------------------------------------
// E100 Stepping Defines - used in PoMgmt Decisions
//-------------------------------------------------------------------------
#define E100_82557_A_STEP   1
#define E100_82557_B_STEP   2
#define E100_82557_C_STEP   3
#define E100_82558_A_STEP   4
#define E100_82558_B_STEP   5
#define E100_82559_A_STEP   6
#define E100_82559_B_STEP   7
#define E100_82559_C_STEP   8
#define E100_82559ER_A_STEP 9

//-------------------------------------------------------------------------
// D100 PORT functions -- lower 4 bits
//-------------------------------------------------------------------------
#define PORT_SOFTWARE_RESET         0
#define PORT_SELFTEST               1
#define PORT_SELECTIVE_RESET        2
#define PORT_DUMP                   3


//-------------------------------------------------------------------------
// CSR field definitions -- Offsets from CSR base
//-------------------------------------------------------------------------
#define SCB_STATUS_LOW_BYTE         0x0
#define SCB_STATUS_HIGH_BYTE        0x1
#define SCB_COMMAND_LOW_BYTE        0x2
#define SCB_COMMAND_HIGH_BYTE       0x3
#define SCB_GENERAL_POINTER         0x4
#define CSR_PORT_LOW_WORD           0x8
#define CSR_PORT_HIGH_WORD          0x0a
#define CSR_FLASH_CONTROL_REG       0x0c
#define CSR_EEPROM_CONTROL_REG      0x0e
#define CSR_MDI_CONTROL_LOW_WORD    0x10
#define CSR_MDI_CONTROL_HIGH_WORD   0x12


//-------------------------------------------------------------------------
// SCB Status Word bit definitions
//-------------------------------------------------------------------------
//- Interrupt status fields
#define SCB_STATUS_MASK         BIT_12_15       // ACK Mask
#define SCB_STATUS_CX           BIT_15          // CU Completed Action Cmd
#define SCB_STATUS_FR           BIT_14          // RU Received A Frame
#define SCB_STATUS_CNA          BIT_13          // CU Became Inactive (IDLE)
#define SCB_STATUS_RNR          BIT_12          // RU Became Not Ready
#define SCB_STATUS_MDI          BIT_11          // MDI read or write done
#define SCB_STATUS_SWI          BIT_10          // Software generated interrupt

//- Interrupt ACK fields
#define SCB_ACK_MASK            (BIT_9 | BIT_12_15 | BIT_8)   // ACK Mask
#define SCB_ALL_INTERRUPT_BITS  BIT_8_15                      // if all the bits are set, no interrupt to be served
#define SCB_ACK_CX              BIT_15          // CU Completed Action Cmd
#define SCB_ACK_FR              BIT_14          // RU Received A Frame
#define SCB_ACK_CNA             BIT_13          // CU Became Inactive (IDLE)
#define SCB_ACK_RNR             BIT_12          // RU Became Not Ready
#define SCB_ACK_MDI             BIT_11          // MDI read or write done
#define SCB_ACK_SWI             BIT_10          // Software generated interrupt
#define SCB_ACK_ER              BIT_9           // Early Receive interrupt
#define SCB_ACK_FCP             BIT_8           // Flow Control Pause interrupt

//- CUS Fields
#define SCB_CUS_MASK            (BIT_6 | BIT_7) // CUS 2-bit Mask
#define SCB_CUS_IDLE            0               // CU Idle
#define SCB_CUS_SUSPEND         BIT_6           // CU Suspended
#define SCB_CUS_ACTIVE          BIT_7           // CU Active

//- RUS Fields
#define SCB_RUS_IDLE            0               // RU Idle
#define SCB_RUS_MASK            BIT_2_5         // RUS 3-bit Mask
#define SCB_RUS_SUSPEND         BIT_2           // RU Suspended
#define SCB_RUS_NO_RESOURCES    BIT_3           // RU Out Of Resources
#define SCB_RUS_READY           BIT_4           // RU Ready
#define SCB_RUS_SUSP_NO_RBDS    (BIT_2 | BIT_5) // RU No More RBDs
#define SCB_RUS_NO_RBDS         (BIT_3 | BIT_5) // RU No More RBDs
#define SCB_RUS_READY_NO_RBDS   (BIT_4 | BIT_5) // RU Ready, No RBDs


//-------------------------------------------------------------------------
// SCB Command Word bit definitions
//-------------------------------------------------------------------------
//- CUC fields
#define SCB_CUC_MASK            BIT_4_6         // CUC 3-bit Mask
#define SCB_CUC_START           BIT_4           // CU Start
#define SCB_CUC_RESUME          BIT_5           // CU Resume
#define SCB_CUC_DUMP_ADDR       BIT_6           // CU Dump Counters Address
#define SCB_CUC_DUMP_STAT       (BIT_4 | BIT_6) // CU Dump statistics counters
#define SCB_CUC_LOAD_BASE       (BIT_5 | BIT_6) // Load the CU base
#define SCB_CUC_DUMP_RST_STAT   BIT_4_6         // CU Dump and reset statistics counters
#define SCB_CUC_STATIC_RESUME   (BIT_5 | BIT_7) // CU Static Resume

//- RUC fields
#define SCB_RUC_MASK            BIT_0_2         // RUC 3-bit Mask
#define SCB_RUC_START           BIT_0           // RU Start
#define SCB_RUC_RESUME          BIT_1           // RU Resume
#define SCB_RUC_ABORT           BIT_2           // RU Abort
#define SCB_RUC_LOAD_HDS        (BIT_0 | BIT_2) // Load RFD Header Data Size
#define SCB_RUC_LOAD_BASE       (BIT_1 | BIT_2) // Load the RU base
#define SCB_RUC_RBD_RESUME      BIT_0_2         // RBD resume

// Interrupt fields (assuming byte addressing)
#define SCB_INT_MASK            BIT_0           // Mask interrupts
#define SCB_SOFT_INT            BIT_1           // Generate a software interrupt


//-------------------------------------------------------------------------
// EEPROM bit definitions
//-------------------------------------------------------------------------
//- EEPROM control register bits
#define EN_TRNF                     0x10    // Enable turnoff
#define EEDO                        0x08    // EEPROM data out
#define EEDI                        0x04    // EEPROM data in (set for writing data)
#define EECS                        0x02    // EEPROM chip select (1=high, 0=low)
#define EESK                        0x01    // EEPROM shift clock (1=high, 0=low)

//- EEPROM opcodes
#define EEPROM_READ_OPCODE          06
#define EEPROM_WRITE_OPCODE         05
#define EEPROM_ERASE_OPCODE         07
#define EEPROM_EWEN_OPCODE          19      // Erase/write enable
#define EEPROM_EWDS_OPCODE          16      // Erase/write disable

//- EEPROM data locations
#define EEPROM_NODE_ADDRESS_BYTE_0  0
#define EEPROM_FLAGS_WORD_3         3
#define EEPROM_FLAG_10MC            BIT_0
#define EEPROM_FLAG_100MC           BIT_1

//-------------------------------------------------------------------------
// MDI Control register bit definitions
//-------------------------------------------------------------------------
#define MDI_DATA_MASK           BIT_0_15        // MDI Data port
#define MDI_REG_ADDR            BIT_16_20       // which MDI register to read/write
#define MDI_PHY_ADDR            BIT_21_25       // which PHY to read/write
#define MDI_PHY_OPCODE          BIT_26_27       // which PHY to read/write
#define MDI_PHY_READY           BIT_28          // PHY is ready for another MDI cycle
#define MDI_PHY_INT_ENABLE      BIT_29          // Assert INT at MDI cycle completion


//-------------------------------------------------------------------------
// MDI Control register opcode definitions
//-------------------------------------------------------------------------
#define MDI_WRITE               1               // Phy Write
#define MDI_READ                2               // Phy read


//-------------------------------------------------------------------------
// D100 Action Commands
//-------------------------------------------------------------------------
#define CB_NOP                  0
#define CB_IA_ADDRESS           1
#define CB_CONFIGURE            2
#define CB_MULTICAST            3
#define CB_TRANSMIT             4
#define CB_LOAD_MICROCODE       5
#define CB_DUMP                 6
#define CB_DIAGNOSE             7


//-------------------------------------------------------------------------
// Command Block (CB) Field Definitions
//-------------------------------------------------------------------------
//- CB Command Word
#define CB_EL_BIT               BIT_15          // CB EL Bit
#define CB_S_BIT                BIT_14          // CB Suspend Bit
#define CB_I_BIT                BIT_13          // CB Interrupt Bit
#define CB_TX_SF_BIT            BIT_3           // TX CB Flexible Mode
#define CB_CMD_MASK             BIT_0_2         // CB 3-bit CMD Mask

//- CB Status Word
#define CB_STATUS_MASK          BIT_12_15       // CB Status Mask (4-bits)
#define CB_STATUS_COMPLETE      BIT_15          // CB Complete Bit
#define CB_STATUS_OK            BIT_13          // CB OK Bit
#define CB_STATUS_UNDERRUN      BIT_12          // CB A Bit
#define CB_STATUS_FAIL          BIT_11          // CB Fail (F) Bit

//misc command bits
#define CB_TX_EOF_BIT           BIT_15          // TX CB/TBD EOF Bit

//-------------------------------------------------------------------------
// Config CB Parameter Fields
//-------------------------------------------------------------------------
#define CB_CFIG_BYTE_COUNT          22          // 22 config bytes
#define CB_SHORT_CFIG_BYTE_COUNT    8           // 8 config bytes

// byte 0 bit definitions
#define CB_CFIG_BYTE_COUNT_MASK     BIT_0_5     // Byte count occupies bit 5-0

// byte 1 bit definitions
#define CB_CFIG_RXFIFO_LIMIT_MASK   BIT_0_4     // RxFifo limit mask
#define CB_CFIG_TXFIFO_LIMIT_MASK   BIT_4_7     // TxFifo limit mask

// byte 3 bit definitions --
#define CB_CFIG_B3_MWI_ENABLE       BIT_0       // Memory Write Invalidate Enable Bit

// byte 4 bit definitions
#define CB_CFIG_RX_MIN_DMA_MASK     BIT_0_6     // Rx minimum DMA count mask

// byte 5 bit definitions
#define CB_CFIG_TX_MIN_DMA_MASK     BIT_0_6     // Tx minimum DMA count mask
#define CB_CFIG_DMBC_EN             BIT_7       // Enable Tx/Rx minimum DMA counts

// byte 6 bit definitions
#define CB_CFIG_LATE_SCB            BIT_0       // Update SCB After New Tx Start
#define CB_CFIG_TNO_INT             BIT_2       // Tx Not OK Interrupt
#define CB_CFIG_CI_INT              BIT_3       // Command Complete Interrupt
#define CB_CFIG_SAVE_BAD_FRAMES     BIT_7       // Save Bad Frames Enabled

// byte 7 bit definitions
#define CB_CFIG_DISC_SHORT_FRAMES   BIT_0       // Discard Short Frames
#define CB_CFIG_URUN_RETRY          BIT_1_2     // Underrun Retry Count

// byte 8 bit definitions
#define CB_CFIG_503_MII             BIT_0       // 503 vs. MII mode

// byte 9 bit definitions -- pre-defined all zeros

// byte 10 bit definitions
#define CB_CFIG_NO_SRCADR           BIT_3       // No Source Address Insertion
#define CB_CFIG_PREAMBLE_LEN        BIT_4_5     // Preamble Length
#define CB_CFIG_LOOPBACK_MODE       BIT_6_7     // Loopback Mode

// byte 11 bit definitions
#define CB_CFIG_LINEAR_PRIORITY     BIT_0_2     // Linear Priority

// byte 12 bit definitions
#define CB_CFIG_LINEAR_PRI_MODE     BIT_0       // Linear Priority mode
#define CB_CFIG_IFS_MASK            BIT_4_7     // CSMA level Interframe Spacing mask