📄 msp430ad.txt
字号:
datai=datai+50;
delaytostart=0;
start=0;
error=0;
while(1)
{
time32=0;
if(savedata[datai]>aveadd)
{ time32++; }
if(savedata[datai+1]>aveadd)
{ time32++; }
if(savedata[datai+2]>aveadd)
{ time32++; }
if(savedata[datai+3]>aveadd)
{ time32++; }
if(savedata[datai+4]>aveadd)
{ time32++; }
if(time32>=4)
{ start=1;break; }
else if(delaytostart<400)
{ delaytostart++; datai++; }
else
{ error=1;break; }
}
if(error==1)
{
enddata[1]=0x11;enddata[2]=0x22;break;
}
if(start==1)
{
datai=datai+7;
for(n=1;n<9;n++)
{
switch(n)
{
case 1: datai=datai+16;break;
case 2: datai=datai+16;break;
case 3: datai=datai+17;break;
case 4: datai=datai+16;break;
case 5: datai=datai+16;break;
case 6: datai=datai+17;break;
case 7: datai=datai+16;break;
case 8: datai=datai+16;break;
}
time32=0;
if(savedata[datai]>aveadd)
{ time32++; }
if(savedata[datai+1]>aveadd)
{ time32++; }
if(savedata[datai+2]>aveadd)
{ time32++; }
if(time32>=2)
{
switch(n)
{
case 1: enddata[1] &= ~0x01;break;
case 2: enddata[1] &= ~0x02;break;
case 3: enddata[1] &= ~0x04;break;
case 4: enddata[1] &= ~0x08;break;
case 5: enddata[1] &= ~0x10;break;
case 6: enddata[1] &= ~0x20;break;
case 7: enddata[1] &= ~0x40;break;
case 8: enddata[1] &= ~0x80;break;
}
}
else
{
switch(n)
{
case 1: enddata[1] |= 0x01;break;
case 2: enddata[1] |= 0x02;break;
case 3: enddata[1] |= 0x04;break;
case 4: enddata[1] |= 0x08;break;
case 5: enddata[1] |= 0x10;break;
case 6: enddata[1] |= 0x20;break;
case 7: enddata[1] |= 0x40;break;
case 8: enddata[1] |= 0x80;break;
}
}
//datai=datai+6;
}
}
//==========================================================================
datai=datai+50;
delaytostart=0;
start=0;
error=0;
while(1)
{
time32=0;
if(savedata[datai]>aveadd)
{ time32++; }
if(savedata[datai+1]>aveadd)
{ time32++; }
if(savedata[datai+2]>aveadd)
{ time32++; }
if(savedata[datai+3]>aveadd)
{ time32++; }
if(savedata[datai+4]>aveadd)
{ time32++; }
if(time32>=4)
{ start=1;break; }
else if(delaytostart<400)
{ delaytostart++; datai++; }
else
{ error=1;break; }
}
if(error==1)
{ enddata[2]=0x22;break; }
if(start==1)
{
datai=datai+7;
for(n=1;n<9;n++)
{
switch(n)
{
case 1: datai=datai+16;break;
case 2: datai=datai+16;break;
case 3: datai=datai+17;break;
case 4: datai=datai+16;break;
case 5: datai=datai+16;break;
case 6: datai=datai+17;break;
case 7: datai=datai+16;break;
case 8: datai=datai+16;break;
}
time32=0;
if(savedata[datai]>aveadd)
{ time32++; }
if(savedata[datai+1]>aveadd)
{ time32++; }
if(savedata[datai+2]>aveadd)
{ time32++; }
if(time32>=2)
{
switch(n)
{
case 1: enddata[2] &= ~0x01;break;
case 2: enddata[2] &= ~0x02;break;
case 3: enddata[2] &= ~0x04;break;
case 4: enddata[2] &= ~0x08;break;
case 5: enddata[2] &= ~0x10;break;
case 6: enddata[2] &= ~0x20;break;
case 7: enddata[2] &= ~0x40;break;
case 8: enddata[2] &= ~0x80;break;
}
}
else
{
switch(n)
{
case 1: enddata[2] |= 0x01;break;
case 2: enddata[2] |= 0x02;break;
case 3: enddata[2] |= 0x04;break;
case 4: enddata[2] |= 0x08;break;
case 5: enddata[2] |= 0x10;break;
case 6: enddata[2] |= 0x20;break;
case 7: enddata[2] |= 0x40;break;
case 8: enddata[2] |= 0x80;break;
}
}
//datai=datai+6;
}
}
//========================================================================================
break;
}//while(1)
}
void Delay(int delaydata)
{
unsigned long i;
for (i = delaydata; i > 0; i--);
}
void InitUST0(void)
{
U0CTL |= SWRST; // USART模块被允许
U0CTL &= ~SYNC;
U0CTL |= CHAR; // 8位字符
U0CTL |= SPB;
U0TCTL |= SSEL0+SSEL1; // ACLK
U0BR1 =0x0d; //0x0A; // 6MHz/2400baut
U0BR0 =0x05; //0x3D;
U0MCTL = 0x24; //06
ME1 |=UTXE0+URXE0; // 使能 USAR01 TXD/RXD
P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD
P3DIR |= 0x10; // P3.4 为输出
U0CTL &= ~SWRST;
//IE1 |=URXIE0;
}
void InitUST1(void)
{
U1CTL |= SWRST; // USART模块被允许
U1CTL &= ~SYNC;
U1CTL |= CHAR; // 8位字符
U1CTL |= SPB;
U1TCTL |= SSEL0+SSEL1; // SMCLK
U1BR1 =0x0d; //0x0A;// 6MHz/2400baut 8MHZ/2400baut//0d
U1BR0 =0x05; //0x3D; //05
U1MCTL =0x24; //12 //24
ME2 |=UTXE1+URXE1; // 使能 USAR01 TXD/RXD
P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
P3DIR |= 0x40; // P3.6 为输出
U1CTL &= ~SWRST;
}
interrupt[USART1RX_VECTOR] void USART1(void) //ADC中断处理程序
{
int romhe;
saveromdata[6]=saveromdata[5];
saveromdata[5]=saveromdata[4];
saveromdata[4]=saveromdata[3];
saveromdata[3]=saveromdata[2];
saveromdata[2]=saveromdata[1];
saveromdata[1]=saveromdata[0];
saveromdata[0]=U1RXBUF;
romhe=saveromdata[6]+saveromdata[5]+saveromdata[4]+saveromdata[3]+saveromdata[2]+saveromdata[1];
romhe = romhe&0x00ff;
if(saveromdata[0]==romhe)
{
recromok=1;
//IE2 &=~URXIE1;
}
}
void InitADC(void)
{
P6SEL = 0xFF; // 所有P6口线均为ADC模块使用
ADC12CTL0 &=~ 0x02; // 在进行设置时首先复位ADC的转换使能
ADC12CTL0 = SHT0_7+MSC+ADC12ON; // 内部振荡器，置位MSC位，因此转换能自动进行
//6=24us 17.375pot 8=46us 9.065pot
//ADC12CTL1 = 0x0204; //0000 0010 0000 0100
// ADC12SC 位触发采样和保持
// 采样脉冲由采样定时器产生
// 时钟源：内部振荡器
// 时钟分频: 1
// 转换模式: 单通道、重复转换
// 选则参考电压和输入管脚
ADC12CTL1 = 0x021c; //0000 00 1 0 000 11 10 0 SMCLK
ADC12MCTL0 |= SREF_0; //Vr+=AVcc,;Vr-=AVss
ADC12MCTL0 |= INCH_3; //select anonalog input
ADC12IE = 0x01; // 使能通道10 转换完成后中断
ADC12CTL0 |= 0x02; // 使能ADC转换
}
interrupt[ADC_VECTOR] void ADC12(void) //ADC中断处理程序
{
ADCMEM[0]=ADCMEM[0]>>3;
savedata[adtime]=ADCMEM[0];
adtime++;
//P1OUT ^=BIT5;
}
void InitSYS(void)
{
int i;
WDTCTL = WDTPW + WDTHOLD;
//WDTCTL = WDT_ADLY_250; // WDT 250ms, ACLK, interval timer
//IE1 |= WDTIE;
BCSCTL1 &= ~XT2OFF; // XT2晶振 0--open
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}while ((IFG1 & OFIFG)); // OSCFault flag still set?
BCSCTL2 |= SELM_2; // MCLK=XT2
BCSCTL2 |= SELS; // SMCLK=XT2
//FCTL2 = FWKEY + FSSEL0 + FN0; // MCLK/2 for Flash Timing Generator
_EINT();
}
/* //n=5
datai=datai+14;
for(n=1;n<9;n++)
{
switch(n)
{
case 1: datai=datai+30;break;
case 2: datai=datai+30;break;
case 3: datai=datai+31;break;
case 4: datai=datai+30;break;
case 5: datai=datai+30;break;
case 6: datai=datai+31;break;
case 7: datai=datai+30;break;
case 8: datai=datai+30;break;
}
*/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -