utra_lib.mdl

两个Nokia研究人员写的W-CDMA的仿真代码。 包含信道编码

	  FontSize		  12
	  FontWeight		  "bold"
	  SourceBlock		  "utra_lib/Receivers/dl_rake"
	  SourceType		  ""
	  N_rake		  "chips_in_slot"
	  nSlot			  "nSlot"
	  nPilot		  "nPilot"
	  th			  "0.1"
	  nFin			  "1"
	  C			  "C"
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	  Orientation		  "left"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_RX_demodulat"
"ion/inter_deinterleaving"
	  SourceType		  ""
	  Int_mode		  "Inter_int_mode"
	  bits_in_frame		  "bits_in_frame"
	  nFrames		  "nFrames"
	  cols			  "cols"
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	  Name			  "inter_interleaving"
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	  Position		  [585, 159, 715, 251]
	  ForegroundColor	  "blue"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio"
"n/inter_interleaving"
	  SourceType		  ""
	  Int_mode		  "Inter_int_mode"
	  bits_in_frame		  "bits_in_frame"
	  nFrames		  "nFrames"
	  cols			  "cols"
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	Block {
	  BlockType		  Reference
	  Name			  "intra_deinterleaving"
	  Ports			  [2, 2, 0, 0, 0]
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	  Orientation		  "left"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_RX_demodulat"
"ion/intra_deinterleaving"
	  SourceType		  ""
	  Int_mode		  "Intra_int_flag"
	  bits_in_frame		  "bits_in_frame"
	  nFrames		  "nFrames"
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	Block {
	  BlockType		  Reference
	  Name			  "intra_interleaving"
	  Ports			  [1, 1, 0, 0, 0]
	  Position		  [740, 159, 870, 251]
	  ForegroundColor	  "blue"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio"
"n/intra_interleaving"
	  SourceType		  ""
	  Int_mode		  "Intra_int_flag"
	  bits_in_frame		  "bits_in_frame"
	  nFrames		  "nFrames"
	  nSlots		  "nSlot"
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	Block {
	  BlockType		  Reference
	  Name			  "modulation"
	  Ports			  [1, 2, 0, 0, 0]
	  Position		  [945, 143, 1040, 207]
	  ForegroundColor	  "blue"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio"
"n/modulation"
	  SourceType		  ""
	  Ndisc			  "bits_in_frame/nSlot+sum(control)"
	  C			  "C"
	  nSlot			  "nSlot"
	}
	Block {
	  BlockType		  Reference
	  Name			  "rate_dematching"
	  Ports			  [2, 2, 0, 0, 0]
	  Position		  [300, 583, 405, 732]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  SourceBlock		  "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/rate_dematching"
	  SourceType		  ""
	  dr_in			  "nFrames*bits_in_frame"
	  dr_out		  "K*(N+nCRC)+nTail"
	  punk			  "0.2"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  Reference
	  Name			  "remove CRC"
	  Ports			  [2, 2, 0, 0, 0]
	  Position		  [45, 583, 130, 732]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  SourceBlock		  "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/remove CRC"
	  SourceType		  ""
	  nReCRC		  "N+nCRC"
	  nCRC			  "nCRC"
	  crc_poly		  "crc_poly"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  Mux
	  Name			  "tail_mux"
	  Ports			  [2, 1, 0, 0, 0]
	  Position		  [420, 155, 425, 255]
	  ShowName		  off
	  FontName		  "helvetica"
	  FontSize		  12
	  Inputs		  "2"
	  DisplayOption		  "bar"
	}
	Line {
	  SrcBlock		  "demodulation"
	  SrcPort		  2
	  DstBlock		  "intra_deinterleaving"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "demodulation"
	  SrcPort		  1
	  DstBlock		  "intra_deinterleaving"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "intra_deinterleaving"
	  SrcPort		  2
	  DstBlock		  "inter_deinterleaving"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "intra_deinterleaving"
	  SrcPort		  1
	  DstBlock		  "inter_deinterleaving"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  1
	  DstBlock		  "demodulation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  3
	  DstBlock		  "demodulation"
	  DstPort		  3
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	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  2
	  DstBlock		  "demodulation"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  4
	  DstBlock		  "demodulation"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "control_mux"
	  SrcPort		  1
	  DstBlock		  "modulation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "inter_interleaving"
	  SrcPort		  1
	  DstBlock		  "intra_interleaving"
	  DstPort		  1
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	Line {
	  SrcBlock		  "intra_interleaving"
	  SrcPort		  1
	  DstBlock		  "control_mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  " add control"
	  SrcPort		  1
	  Points		  [90, 0]
	  DstBlock		  "control_mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "inter_deinterleaving"
	  SrcPort		  2
	  DstBlock		  "rate_dematching"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "rate_dematching"
	  SrcPort		  2
	  DstBlock		  "ch_decoding"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "rate_dematching"
	  SrcPort		  1
	  DstBlock		  "ch_decoding"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ch_decoding"
	  SrcPort		  2
	  DstBlock		  "remove CRC"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "ch_decoding"
	  SrcPort		  1
	  DstBlock		  "remove CRC"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Rate Matching"
	  SrcPort		  1
	  DstBlock		  "inter_interleaving"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "ch_coding"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Add CRC2"
	  SrcPort		  1
	  DstBlock		  "ch_coding"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ch_coding"
	  SrcPort		  1
	  DstBlock		  "tail_mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ch_coding"
	  SrcPort		  2
	  DstBlock		  "tail_mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "tail_mux"
	  SrcPort		  1
	  DstBlock		  "Rate Matching"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "inter_deinterleaving"
	  SrcPort		  1
	  DstBlock		  "rate_dematching"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "channel2"
	  SrcPort		  4
	  Points		  [0, 295]
	  DstBlock		  "dl_rake"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "Channel estimator"
	  SrcPort		  3
	  Points		  [0, 160]
	  DstBlock		  "dl_rake"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "Channel estimator"
	  SrcPort		  1
	  Points		  [0, 100]
	  DstBlock		  "dl_rake"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Channel estimator"
	  SrcPort		  2
	  Points		  [0, 130]
	  DstBlock		  "dl_rake"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "channel2"
	  SrcPort		  3
	  DstBlock		  "Channel estimator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "channel2"
	  SrcPort		  2
	  DstBlock		  "Channel estimator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "remove CRC"
	  SrcPort		  2
	  Points		  [-5, 0]
	  DstBlock		  "To Workspace24"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "remove CRC"
	  SrcPort		  1
	  Points		  [-10, 0; 0, -120]
	  DstBlock		  "Delayed ber calculation1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "data source 01 ..10"
	  SrcPort		  1
	  Points		  [0, 55]
	  Branch {
	    Points		    [0, 5]
	    DstBlock		    "Add CRC2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 275]
	    DstBlock		    "Delayed ber calculation1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "channel2"
	  SrcPort		  1
	  Points		  [0, 175]
	  DstBlock		  "dl_rake"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "modulation"
	  SrcPort		  1
	  Points		  [40, 0]
	  DstBlock		  "channel2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "modulation"
	  SrcPort		  2
	  Points		  [105, 0]
	  DstBlock		  "channel2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Delayed ber calculation1"
	  SrcPort		  1
	  DstBlock		  "To Workspace23"
	  DstPort		  1
	}
	Annotation {
	  Position		  [200, 97]
	  Text			  "N = input block size"
	}
	Annotation {
	  Position		  [775, 420]
	  Text			  "input_block_size (=N) = is the number of bi"
"ts in each input block\nnFrames = number of frames in each block\nnCRC = numb"
"er of CRC bits added before channel coding\ncType = coding type\nK = coding r"
"atio\nnTail = number of tail bits\nch_poly is a vector of polynomial for chan"
"nel coding\nbits_in_frame = number of coded bits in a frame\nInter_int_mode ="
" indicates what kind of inter frame interleaver is used\ncols = number of col"
"umns for block interleaver (if used)\nIntra_int_flag = indicates ifintre fram"
"e interleaver is used or not\nnSlot = number of slots in a frame\n\nchips_in_"
"slot = number of chips in one slot\n                                         "
"              This is the channel and receiver model input size\nnPilot = Num"
"ber of pilot bits (removed at receiver)\nTPC = number of Power contro bits\nT"
"FI = number of TFI bits\nC = spreading code\n"
	}
	Annotation {
	  Position		  [328, 328]
	  Text			  "DO NOT CHANGE THESE PARAMETER VALUES!!\nTHE"
"Y ARE CALCULATED IN THE MASK OF THIS SUBSYSTEM\n(Change the values at upper l"
"evel \nEdit dl_start.m file only if necessaary)"
	  FontName		  "helvetica"
	  FontSize		  12
	  FontWeight		  "bold"
	}
	Annotation {
	  Position		  [1068, 72]
	  Text			  "PARAMETERS WHICH CAN BE EDITED IN THIS VIEW"
"\nare inte following blocks:\n\nCHANNEL block \nRAKE RECEIVER block\n\nNOTE: "
"change only the numberical values"
	}
      }
    }
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