utra_lib.mdl

两个Nokia研究人员写的W-CDMA的仿真代码。 包含信道编码

	  chCode		  "chCode"
	}
	Block {
	  BlockType		  Reference
	  Name			  "dl_TX_modulation"
	  Ports			  [1, 2, 0, 0, 0]
	  Position		  [440, 35, 630, 155]
	  ForegroundColor	  "yellow"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio"
"n"
	  SourceType		  "Unknown"
	  sizes			  "sizes"
	  control		  "control"
	  C			  "C"
	  Inter_int_mode	  "Inter_int_mode"
	  cols			  "cols"
	  Intra_int_flag	  "Intra_int_flag"
	}
	Block {
	  BlockType		  Reference
	  Name			  "dl_rake"
	  Ports			  [5, 4, 0, 0, 0]
	  Position		  [660, 382, 920, 528]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  FontName		  "helvetica"
	  FontSize		  12
	  FontWeight		  "bold"
	  SourceBlock		  "utra_lib/Receivers/dl_rake"
	  SourceType		  "Unknown"
	  N_rake		  "chips_in_slot"
	  nSlot			  "nSlot"
	  nPilot		  "nPilot"
	  th			  "0.1"
	  nFin			  "1"
	  C			  "C"
	}
	Block {
	  BlockType		  Outport
	  Name			  "I-siganl"
	  Position		  [705, 60, 735, 70]
	  Port			  "1"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "[]"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Q-signal"
	  Position		  [705, 118, 735, 132]
	  Port			  "2"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "[]"
	}
	Block {
	  BlockType		  Outport
	  Name			  "ber"
	  Position		  [440, 223, 470, 237]
	  Port			  "3"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "[]"
	}
	Block {
	  BlockType		  Outport
	  Name			  "crc"
	  Position		  [95, 490, 125, 500]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  Port			  "4"
	  OutputWhenDisabled	  "held"
	  InitialOutput		  "[]"
	}
	Line {
	  SrcBlock		  "I -signalI"
	  SrcPort		  1
	  DstBlock		  "dl_rake"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "channel"
	  SrcPort		  1
	  DstBlock		  "dl_rake"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "delay"
	  SrcPort		  1
	  DstBlock		  "dl_rake"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "nTaps"
	  SrcPort		  1
	  DstBlock		  "dl_rake"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "Q - signal"
	  SrcPort		  1
	  DstBlock		  "dl_rake"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "dl_RX_channel_decoding"
	  SrcPort		  2
	  DstBlock		  "crc"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  4
	  DstBlock		  "dl_RX_demodulation"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  3
	  DstBlock		  "dl_RX_demodulation"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  2
	  DstBlock		  "dl_RX_demodulation"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "dl_rake"
	  SrcPort		  1
	  DstBlock		  "dl_RX_demodulation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_RX_demodulation"
	  SrcPort		  1
	  DstBlock		  "dl_RX_channel_decoding"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_RX_demodulation"
	  SrcPort		  2
	  DstBlock		  "dl_RX_channel_decoding"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "dl_RX_channel_decoding"
	  SrcPort		  1
	  Points		  [-50, 0; 0, -170]
	  DstBlock		  "Delayed ber calculation1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "dl_TX_channel_coding"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "dl_TX_channel_coding"
	  SrcPort		  1
	  DstBlock		  "dl_TX_modulation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delayed ber calculation1"
	  SrcPort		  1
	  DstBlock		  "ber"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "data source 01 ..10"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "dl_TX_channel_coding"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 140]
	    DstBlock		    "Delayed ber calculation1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "dl_TX_modulation"
	  SrcPort		  1
	  DstBlock		  "I-siganl"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "dl_TX_modulation"
	  SrcPort		  2
	  DstBlock		  "Q-signal"
	  DstPort		  1
	}
	Annotation {
	  Position		  [900, 205]
	  Text			  "input_block_size (=N) = is the number of bi"
"ts in each input block\nnCRC = number of CRC bits added before channel coding"
"\nchips_in_slot = number of chips in one slot\n                              "
"                         This is the channel and receiver model input size\nn"
"Pilot = Number of pilot bits (removed at receiver)"
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "DL_open"
      Ports		      [0, 0, 0, 0, 0]
      Position		      [296, 35, 505, 216]
      Orientation	      "left"
      FontName		      "helvetica"
      ShowPortLabels	      on
      MaskPromptString	      "TX channel Type|Channel coding  |Coding ratio  "
"     |Spreading code length|Inter frame interleaver |Number of frames for int"
"er frame interleaver|Number of columns for inter frame interleaver |Intra fra"
"me interleaver (on or off)"
      MaskStyleString	      "popup(Dedicated Transport channel|Primary commo"
"n control|Secondary common control (FACH or PCH)),popup(Convolutional coding|"
"Turbo),popup(2|3),popup(4|8|16|32|64|128|256),popup(block interleaver|multist"
"age interleaver),edit,edit,checkbox"
      MaskTunableValueString  "on,on,on,on,on,on,on,on"
      MaskCallbackString      "|||||||"
      MaskEnableString	      "on,on,on,on,on,on,on,on"
      MaskVisibilityString    "on,on,on,on,on,on,on,on"
      MaskVariables	      "tx_ch=@1;cType=@2;Kindex=@3;nC=@4;Inter_int_mod"
"e=@5;nFrames=@6;cols=@7;Intra_int_flag=@8;"
      MaskInitialization      "nCode=2^(nC+1);\n      % if you want to specify"
" which code is used define ncode=[nCode index]\n[sizes,crc,chCode,C,control]="
"dl_start(nCode,cType,Kindex,nFrames,tx_ch);\ninput_block_size=sizes(1);N=inpu"
"t_block_size;bits_in_frame=sizes(2);nFrames=sizes(3);\nnSlot=sizes(5); chips_"
"in_slot=sizes(6);nCRC=crc(1);crc_poly=crc(2);\ncType=chCode(1);K=chCode(2); n"
"Tail=chCode(3);ch_poly=[chCode(4:6)];\nnPilot=control(1);TPC=control(2);TFI=c"
"ontrol(3);"
      MaskDisplay	      "disp('DOWNLINK - open \\n\\nTransportChannel\\n"
"\\n\\n\\n\\n1 - Decicated transport \nchannel\\n2 - Primary common control ch"
"annel\\n3 - Secondary common control channel')\ndisp(tx_ch)"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      MaskValueString	      "Dedicated Transport channel|Convolutional codin"
"g|2|256|block interleaver|1|1|off"
      System {
	Name			"DL_open"
	Location		[-254, 101, 976, 972]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	AutoZoom		on
	Block {
	  BlockType		  Reference
	  Name			  " add control"
	  Ports			  [0, 1, 0, 0, 0]
	  Position		  [675, 62, 790, 138]
	  FontName		  "helvetica"
	  FontSize		  12
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_TX_modulatio"
"n/ add control"
	  SourceType		  ""
	  nPilot		  "nPilot"
	  nPower		  "TPC"
	  nTFI			  "TFI"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Add CRC2"
	  Ports			  [1, 1, 0, 0, 0]
	  Position		  [100, 152, 190, 208]
	  ShowName		  off
	  FontName		  "helvetica"
	  SourceBlock		  "utra_lib/Channel coding block/dl_TX_channel"
"_coding/Add CRC2"
	  SourceType		  ""
	  N			  "N"
	  nCRC			  "nCRC"
	  crc_poly		  "crc_poly"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Channel estimator"
	  Ports			  [2, 3, 0, 0, 0]
	  Position		  [1082, 450, 1148, 520]
	  Orientation		  "down"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  ShowName		  off
	  SourceBlock		  "utra_lib/Channel models/Channel estimator"
	  SourceType		  ""
	  threshold		  "0.05"
	  nSlot			  "nSlot"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [120, 214, 190, 246]
	  ShowName		  off
	  Value			  "N+nCRC"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delayed ber calculation1"
	  Ports			  [2, 1, 0, 0, 0]
	  Position		  [85, 427, 285, 523]
	  SourceBlock		  "utra_lib/Test functions/Delayed ber calcula"
"tion"
	  SourceType		  ""
	  N			  "N"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Rate Matching"
	  Ports			  [1, 1, 0, 0, 0]
	  Position		  [470, 179, 555, 231]
	  SourceBlock		  "utra_lib/Channel coding block/dl_TX_channel"
"_coding/Rate Matching"
	  SourceType		  ""
	  r_in			  "K*(N+nCRC)+nTail"
	  r_out			  "nFrames*bits_in_frame"
	  punk			  "0.2"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  ToWorkspace
	  Name			  "To Workspace23"
	  Position		  [315, 460, 375, 490]
	  ShowName		  off
	  VariableName		  "ber"
	  Buffer		  "inf"
	  Decimation		  "1"
	  SampleTime		  "nFrames"
	  SaveFormat		  "Matrix"
	}
	Block {
	  BlockType		  ToWorkspace
	  Name			  "To Workspace24"
	  Position		  [50, 740, 110, 770]
	  ShowName		  off
	  VariableName		  "crc"
	  Buffer		  "inf"
	  Decimation		  "1"
	  SampleTime		  "nFrames"
	  SaveFormat		  "Matrix"
	}
	Block {
	  BlockType		  Reference
	  Name			  "ch_coding"
	  Ports			  [2, 2, 0, 0, 0]
	  Position		  [235, 157, 375, 253]
	  ForegroundColor	  "blue"
	  SourceBlock		  "utra_lib/Channel coding block/dl_TX_channel"
"_coding/ch_coding"
	  SourceType		  "wcdma"
	  N_chcode		  "N+nCRC"
	  cType			  "cType"
	  K			  "K"
	  nTail			  "nTail"
	  poly			  "ch_poly"
	  nFrames		  "nFrames"
	}
	Block {
	  BlockType		  Reference
	  Name			  "ch_decoding"
	  Ports			  [2, 2, 0, 0, 0]
	  Position		  [165, 581, 265, 734]
	  Orientation		  "left"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  SourceBlock		  "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/ch_decoding"
	  SourceType		  "wcdma"
	  N_chdecode		  "(nCRC+N)*K+nTail"
	  cType			  "cType"
	  K			  "K"
	  nTail			  "nTail"
	  poly			  "ch_poly"
	  nFrames		  "nFrames"
	  sp0			  "[1 0]"
	  sp1			  "[ 0 1]"
	}
	Block {
	  BlockType		  Reference
	  Name			  "channel2"
	  Ports			  [2, 4, 0, 0, 0]
	  Position		  [1050, 255, 1185, 415]
	  Orientation		  "down"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  ShowName		  off
	  FontName		  "helvetica"
	  FontWeight		  "bold"
	  SourceBlock		  "utra_lib/Channel models/channel2"
	  SourceType		  ""
	  N			  "chips_in_slot"
	  nSlot			  "nSlot"
	  RM			  "[0.9 0 0.1]"
	  DM			  "[0 1 2]"
	  HP			  "1"
	  snr			  "0"
	  P			  "0"
	  nCode			  "length(C)"
	  in_type		  "integer"
	}
	Block {
	  BlockType		  Mux
	  Name			  "control_mux"
	  Ports			  [2, 1, 0, 0, 0]
	  Position		  [900, 108, 905, 237]
	  ShowName		  off
	  FontName		  "helvetica"
	  FontSize		  12
	  Inputs		  "2"
	  DisplayOption		  "bar"
	}
	Block {
	  BlockType		  Reference
	  Name			  "data source 01 ..10"
	  Ports			  [0, 1, 0, 0, 0]
	  Position		  [17, 75, 103, 115]
	  Orientation		  "down"
	  NamePlacement		  "alternate"
	  ShowName		  off
	  SourceBlock		  "utra_lib/Source blocks/data source 01 ..10"
	  SourceType		  "koe"
	  nFrames		  "nFrames"
	  N			  "N"
	}
	Block {
	  BlockType		  Reference
	  Name			  "demodulation"
	  Ports			  [4, 2, 0, 0, 0]
	  Position		  [710, 579, 825, 731]
	  Orientation		  "left"
	  ForegroundColor	  "blue"
	  NamePlacement		  "alternate"
	  FontName		  "helvetica"
	  SourceBlock		  "utra_lib/Modulation  blocks/dl_RX_demodulat"
"ion/demodulation"
	  SourceType		  ""
	  nBuff_in		  "bits_in_frame/nSlot + TPC+TFI"
	  nBuff_out		  "bits_in_frame"
	  nSlot			  "nSlot"
	  nControl		  "TPC+TFI"
	}
	Block {
	  BlockType		  Reference
	  Name			  "dl_rake"
	  Ports			  [5, 4, 0, 0, 0]
	  Position		  [865, 576, 1040, 734]
	  Orientation		  "left"
	  NamePlacement		  "alternate"
	  FontName		  "helvetica"