mp3.lst

diy硬盘mp3的程序

__text_start:
__start:
    00FB EFCF      LDI	R28,0xFF
    00FC E1D0      LDI	R29,0x10
    00FD BFCD      OUT	0x3D,R28
    00FE BFDE      OUT	0x3E,R29
    00FF 58C0      SUBI	R28,0x80
    0100 40D0      SBCI	R29,0
    0101 EA0A      LDI	R16,0xAA
    0102 8308      STD	Y+0,R16
    0103 2400      CLR	R0
    0104 E6E6      LDI	R30,0x66
    0105 E0F1      LDI	R31,1
    0106 E015      LDI	R17,5
    0107 3BE0      CPI	R30,0xB0
    0108 07F1      CPC	R31,R17
    0109 F011      BEQ	0x010C
    010A 9201      ST	R0,Z+
    010B CFFB      RJMP	0x0107
    010C 8300      STD	Z+0,R16
    010D E8EF      LDI	R30,0x8F
    010E E0F1      LDI	R31,1
    010F E0A0      LDI	R26,0
    0110 E0B1      LDI	R27,1
    0111 E011      LDI	R17,1
    0112 3FE5      CPI	R30,0xF5
    0113 07F1      CPC	R31,R17
    0114 F021      BEQ	0x0119
    0115 95C8      LPM
    0116 9631      ADIW	R30,1
    0117 920D      ST	R0,X+
    0118 CFF9      RJMP	0x0112
    0119 940E07B3  CALL	_main
_exit:
    011B CFFF      RJMP	_exit
_init_ata:
  j                    --> Y+1
  i                    --> Y+1
  word_read            --> Y+1
  device               --> R20
    011C 940E154B  CALL	push_gset2
    011E 2F40      MOV	R20,R16
FILE: C:\DATA\MP3\Player\Code2\ata.c
(0001) #include <iom128v.h>
(0002) #include <string.h>
(0003) #include <stdio.h>
(0004) #include <macros.h>
(0005) #include "ata.h"
(0006) #include "generic.h"
(0007) #include "remote.h"
(0008) 
(0009) #define debug
(0010) #define debugport 1
(0011) 
(0012) //******************************************************************
(0013) //*	INITIALIZE HARDWARE FOR ATA DRIVER
(0014) //*   
(0015) //*   
(0016) //******************************************************************
(0017) int init_ata(unsigned char device)
(0018) {
(0019) unsigned int word_read,i,j;
(0020) 
(0021) ata_databus_in;
    011F 2422      CLR	R2
    0120 BA2A      OUT	0x1A,R2
    0121 BA24      OUT	0x14,R2
(0022) PORT_ATA_IO_CNTL_DDR = 0xff;
    0122 EF8F      LDI	R24,0xFF
    0123 93800061  STS	0x61,R24
(0023) PORT_ATA_IO_CNTL = ATA_IO_HIZ;
    0125 93800062  STS	0x62,R24
(0024) PORT_ATA_RST_CNTL_DDR |= ATA_RESET;
    0127 91800064  LDS	R24,0x64
    0129 6082      ORI	R24,2
    012A 93800064  STS	0x64,R24
(0025) 
(0026) ata_hard_reset();
    012C D03D      RCALL	_ata_hard_reset
(0027) 
(0028) while (!ready & busy);
    012D D10D      RCALL	_ata_rdy
    012E 2300      TST	R16
    012F F419      BNE	0x0133
    0130 E061      LDI	R22,1
    0131 E070      LDI	R23,0
    0132 C002      RJMP	0x0135
    0133 2766      CLR	R22
    0134 2777      CLR	R23
    0135 D10D      RCALL	_ata_bsy
    0136 2E20      MOV	R2,R16
    0137 2433      CLR	R3
    0138 012B      MOVW	R4,R22
    0139 2042      AND	R4,R2
    013A 2053      AND	R5,R3
    013B 2044      TST	R4
    013C F781      BNE	0x012D
    013D 2055      TST	R5
    013E F771      BNE	0x012D
(0029) ata_select_device(device);
    013F 2F04      MOV	R16,R20
    0140 D03E      RCALL	_ata_select_device
(0030) while (!ready & busy);
    0141 D0F9      RCALL	_ata_rdy
    0142 2300      TST	R16
    0143 F419      BNE	0x0147
    0144 E061      LDI	R22,1
    0145 E070      LDI	R23,0
    0146 C002      RJMP	0x0149
    0147 2766      CLR	R22
    0148 2777      CLR	R23
    0149 D0F9      RCALL	_ata_bsy
    014A 2E20      MOV	R2,R16
    014B 2433      CLR	R3
    014C 012B      MOVW	R4,R22
    014D 2042      AND	R4,R2
    014E 2053      AND	R5,R3
    014F 2044      TST	R4
    0150 F781      BNE	0x0141
    0151 2055      TST	R5
    0152 F771      BNE	0x0141
(0031) ata_write_byte(ATA_IO_CMD,CMD_RECALIBRATE);
    0153 E120      LDI	R18,0x10
    0154 EF0D      LDI	R16,0xFD
    0155 D084      RCALL	_ata_write_byte
(0032) while (busy);
    0156 D0EC      RCALL	_ata_bsy
    0157 2300      TST	R16
    0158 F7E9      BNE	0x0156
(0033) ata_write_byte(ATA_IO_SECTORCNT,60); // Sleep after 5 min
    0159 E32C      LDI	R18,0x3C
    015A EE05      LDI	R16,0xE5
    015B D07E      RCALL	_ata_write_byte
(0034) while (busy);
    015C D0E6      RCALL	_ata_bsy
    015D 2300      TST	R16
    015E F7E9      BNE	0x015C
(0035) ata_write_byte(ATA_IO_CMD,CMD_STANDBY2);
    015F E926      LDI	R18,0x96
    0160 EF0D      LDI	R16,0xFD
    0161 D078      RCALL	_ata_write_byte
(0036) while (busy);
    0162 D0E0      RCALL	_ata_bsy
    0163 2300      TST	R16
    0164 F7E9      BNE	0x0162
(0037) 
(0038) return 1;
    0165 E001      LDI	R16,1
    0166 E010      LDI	R17,0
    0167 940E1528  CALL	pop_gset2
    0169 9508      RET
(0039) }
(0040) 
(0041) //******************************************************************
(0042) //*	PERFORM HARDWARE RESET
(0043) //*   This routine toggles ATA RESET line low for 10ms.
(0044) //*   
(0045) //******************************************************************										 									 									 
(0046) void ata_hard_reset(void)
(0047) {
(0048) ata_databus_in;
_ata_hard_reset:
    016A 2422      CLR	R2
    016B BA2A      OUT	0x1A,R2
    016C BA24      OUT	0x14,R2
(0049) PORT_ATA_RST_CNTL &= ~ATA_RESET;
    016D 91800065  LDS	R24,0x65
    016F 7F8D      ANDI	R24,0xFD
    0170 93800065  STS	0x65,R24
(0050) delay_ms(10);
    0172 E00A      LDI	R16,0xA
    0173 E010      LDI	R17,0
    0174 940E0787  CALL	_delay_ms
(0051) PORT_ATA_RST_CNTL |= ATA_RESET;
    0176 91800065  LDS	R24,0x65
    0178 6082      ORI	R24,2
    0179 93800065  STS	0x65,R24
(0052) delay_ms(10);
    017B E00A      LDI	R16,0xA
    017C E010      LDI	R17,0
(0053) }   
    017D 940C0787  JMP	_delay_ms
_ata_select_device:
  device               --> R20
    017F 940E1534  CALL	push_gset1
    0181 2F40      MOV	R20,R16
(0054) 
(0055) //******************************************************************
(0056) //*	SELECT ATA DEVICE
(0057) //*   This routine defaults to Drive 0 as the target drive.
(0058) //*   
(0059) //******************************************************************
(0060) void ata_select_device(unsigned char device)
(0061) {
(0062) switch (device)
    0182 2755      CLR	R21
    0183 3040      CPI	R20,0
    0184 0745      CPC	R20,R21
    0185 F029      BEQ	0x018B
    0186 3041      CPI	R20,1
    0187 E0E0      LDI	R30,0
    0188 075E      CPC	R21,R30
    0189 F029      BEQ	0x018F
    018A C008      RJMP	0x0193
(0063) 	{
(0064)    	case 0x00:
(0065) 		ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
    018B EE20      LDI	R18,0xE0
    018C EF05      LDI	R16,0xF5
    018D D04C      RCALL	_ata_write_byte
(0066) 		break;
    018E C007      RJMP	0x0196
(0067)   	case 0x01:
(0068) 		ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV1);
    018F EF20      LDI	R18,0xF0
    0190 EF05      LDI	R16,0xF5
    0191 D048      RCALL	_ata_write_byte
(0069) 		break;
    0192 C003      RJMP	0x0196
(0070) 	default:
(0071) 		ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
    0193 EE20      LDI	R18,0xE0
    0194 EF05      LDI	R16,0xF5
    0195 D044      RCALL	_ata_write_byte
(0072) 		break;
(0073)   }
(0074) }
    0196 940E1537  CALL	pop_gset1
    0198 9508      RET
_ata_write_word:
  wordout              --> R20
  reg                  --> R22
    0199 940E154B  CALL	push_gset2
    019B 01A9      MOVW	R20,R18
    019C 2F60      MOV	R22,R16
(0075) 
(0076) //******************************************************************
(0077) //*	WRITE WORD TO ATA DEVICE
(0078) //*   
(0079) //* Mapping : D0-PA0,D1-PA2,D2-PA4,D3-PA6,D4-PC7,D5-PC5,D7-PC3,D7-PC1
(0080) //*			  D8-PC0,D9-PC2,D10-PC4,D11-PC6,D12-PA7,D13-PA5,D14-PA3,D15-PA1
(0081) //******************************************************************										 									 									 
(0082) void ata_write_word(unsigned char reg,unsigned int wordout)
(0083) {
(0084) WDR();
    019D 95A8      WDR
(0085) PORT_ATA_IO_CNTL = reg;
    019E 93600062  STS	0x62,R22
(0086) 
(0087) ata_databus_out;
    01A0 EF8F      LDI	R24,0xFF
    01A1 BB8A      OUT	0x1A,R24
    01A2 BB84      OUT	0x14,R24
(0088) 
(0089) PORT_ATA_DATA1_OUT = 0x00;
    01A3 2422      CLR	R2
    01A4 BA2B      OUT	0x1B,R2
(0090) PORT_ATA_DATA2_OUT = 0x00;
    01A5 BA25      OUT	0x15,R2
(0091) 
(0092) if (wordout & 0x0001) PORT_ATA_DATA1_OUT |= 0x01; 
    01A6 FD40      SBRC	R20,0
    01A7 9AD8      SBI	0x1B,0
(0093) if (wordout & 0x0002) PORT_ATA_DATA1_OUT |= 0x04;
    01A8 FD41      SBRC	R20,1
    01A9 9ADA      SBI	0x1B,2
(0094) if (wordout & 0x0004) PORT_ATA_DATA1_OUT |= 0x10;
    01AA FD42      SBRC	R20,2
    01AB 9ADC      SBI	0x1B,4
(0095) if (wordout & 0x0008) PORT_ATA_DATA1_OUT |= 0x40;
    01AC FD43      SBRC	R20,3
    01AD 9ADE      SBI	0x1B,6
(0096) if (wordout & 0x0010) PORT_ATA_DATA2_OUT |= 0x80;
    01AE FD44      SBRC	R20,4
    01AF 9AAF      SBI	0x15,7
(0097) if (wordout & 0x0020) PORT_ATA_DATA2_OUT |= 0x20;
    01B0 FD45      SBRC	R20,5
    01B1 9AAD      SBI	0x15,5
(0098) if (wordout & 0x0040) PORT_ATA_DATA2_OUT |= 0x08;
    01B2 FD46      SBRC	R20,6
    01B3 9AAB      SBI	0x15,3
(0099) if (wordout & 0x0080) PORT_ATA_DATA2_OUT |= 0x02;
    01B4 FD47      SBRC	R20,7
    01B5 9AA9      SBI	0x15,1
(0100) if (wordout & 0x0100) PORT_ATA_DATA2_OUT |= 0x01;
    01B6 FD50      SBRC	R21,0
    01B7 9AA8      SBI	0x15,0
(0101) if (wordout & 0x0200) PORT_ATA_DATA2_OUT |= 0x04;
    01B8 FD51      SBRC	R21,1
    01B9 9AAA      SBI	0x15,2
(0102) if (wordout & 0x0400) PORT_ATA_DATA2_OUT |= 0x10;
    01BA FD52      SBRC	R21,2
    01BB 9AAC      SBI	0x15,4
(0103) if (wordout & 0x0800) PORT_ATA_DATA2_OUT |= 0x40;
    01BC FD53      SBRC	R21,3
    01BD 9AAE      SBI	0x15,6
(0104) if (wordout & 0x1000) PORT_ATA_DATA1_OUT |= 0x80;
    01BE FD54      SBRC	R21,4
    01BF 9ADF      SBI	0x1B,7
(0105) if (wordout & 0x2000) PORT_ATA_DATA1_OUT |= 0x20;
    01C0 FD55      SBRC	R21,5
    01C1 9ADD      SBI	0x1B,5
(0106) if (wordout & 0x4000) PORT_ATA_DATA1_OUT |= 0x08;
    01C2 FD56      SBRC	R21,6
    01C3 9ADB      SBI	0x1B,3
(0107) if (wordout & 0x8000) PORT_ATA_DATA1_OUT |= 0x02;
    01C4 FD57      SBRC	R21,7
    01C5 9AD9      SBI	0x1B,1
(0108) 
(0109) ata_write_pulse;
    01C6 91800062  LDS	R24,0x62
    01C8 778F      ANDI	R24,0x7F
    01C9 93800062  STS	0x62,R24
    01CB E001      LDI	R16,1
    01CC E010      LDI	R17,0
    01CD 940E079D  CALL	_delay_us
    01CF 91800062  LDS	R24,0x62
    01D1 6880      ORI	R24,0x80
    01D2 93800062  STS	0x62,R24
(0110) 
(0111) ata_databus_in;
    01D4 2422      CLR	R2
    01D5 BA2A      OUT	0x1A,R2
    01D6 BA24      OUT	0x14,R2
(0112) } 	
    01D7 940E1528  CALL	pop_gset2
    01D9 9508      RET
_ata_write_byte:
  byteout              --> R22
  reg                  --> R20
    01DA 940E154B  CALL	push_gset2
    01DC 2F62      MOV	R22,R18
    01DD 2F40      MOV	R20,R16
(0113) 
(0114) //******************************************************************
(0115) //*	WRITE BYTE TO ATA DEVICE
(0116) //*   
(0117) //*
(0118) //******************************************************************										 									 									 
(0119) void ata_write_byte(unsigned char reg,unsigned char byteout)
(0120) {
(0121) ata_write_word(reg,(unsigned int)byteout);
    01DE 2F26      MOV	R18,R22
    01DF 2733      CLR	R19
    01E0 2F04      MOV	R16,R20
    01E1 DFB7      RCALL	_ata_write_word
(0122) }
    01E2 940E1528  CALL	pop_gset2
    01E4 9508      RET
_ata_read_word:
  wordin               --> R20
  reg                  --> R22
    01E5 940E154B  CALL	push_gset2
    01E7 2F60      MOV	R22,R16
(0123) 
(0124) //******************************************************************
(0125) //*	READ WORD FROM ATA DEVICE
(0126) //*   
(0127) //*   
(0128) //* Mapping : D0-PA0,D1-PA2,D2-PA4,D3-PA6,D4-PC7,D5-PC5,D7-PC3,D7-PC1
(0129) //*			  D8-PC0,D9-PC2,D10-PC4,D11-PC6,D12-PA7,D13-PA5,D14-PA3,D15-PA1
(0130) //******************************************************************										 									 									 
(0131) unsigned int ata_read_word(unsigned char reg)
(0132) {
(0133) unsigned int wordin = 0;
    01E8 2744      CLR	R20
    01E9 2755      CLR	R21
(0134) 
(0135) WDR();
    01EA 95A8      WDR
(0136) PORT_ATA_IO_CNTL = reg;
    01EB 93600062  STS	0x62,R22
(0137) 
(0138) ata_databus_in;
    01ED 2422      CLR	R2
    01EE BA2A      OUT	0x1A,R2
    01EF BA24      OUT	0x14,R2
(0139) 
(0140) PORT_ATA_IO_CNTL &= ~ATA_IOR;
    01F0 91800062  LDS	R24,0x62
    01F2 7B8F      ANDI	R24,0xBF
    01F3 93800062  STS	0x62,R24
(0141) delay_us(1);
    01F5 E001      LDI	R16,1
    01F6 E010      LDI	R17,0
    01F7 940E079D  CALL	_delay_us
(0142) 
(0143) if (PORT_ATA_DATA1_IN & 0x01) wordin |= 0x0001;
    01F9 9BC8      SBIS	0x19,0
    01FA C001      RJMP	0x01FC
    01FB 6041      ORI	R20,1
(0144) if (PORT_ATA_DATA1_IN & 0x02) wordin |= 0x8000;
    01FC 9BC9      SBIS	0x19,1
    01FD C001      RJMP	0x01FF
    01FE 6850      ORI	R21,0x80
(0145) if (PORT_ATA_DATA1_IN & 0x04) wordin |= 0x0002;
    01FF 9BCA      SBIS	0x19,2
    0200 C001      RJMP	0x0202
    0201 6042      ORI	R20,2
(0146) if (PORT_ATA_DATA1_IN & 0x08) wordin |= 0x4000;