📄 dk3200_1_demo.lst
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C51 COMPILER V7.00 DK3200_1_DEMO 01/21/2003 14:51:26 PAGE 1
C51 COMPILER V7.00, COMPILATION OF MODULE DK3200_1_DEMO
OBJECT MODULE PLACED IN DK3200_1_demo.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE DK3200_1_demo.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 /*------------------------------------------------------------------------------
2 DK3200_1_demo.c
3
4 Simple Demo code for uPSD, see App Note AN1560
5 PWM channel PWM0 outputs pulse train that is integrated by RC circuit on DK3000 board
6 to produce a DC voltage which is read by ADC channel ADC0. The PW duty cycle varies to
7 produce a slow DC voltage swing between 0 and 5VDC. The ADC conversion value is
8 displayed in HEX format on the LCD, showing values between 0x00 and 0xFF as the voltage
9 swings. Jumpers must be installed on DK3000 JP1 pins 23 to 24, and on pins 15 to 16,
10 which wraps PWM0 output into ADC0 input.
11
12 This program also demonstrates using a 4-bit auto-reloading down-counter in the PLD
13 of the uPSD. The 8032 can set the initial down-count value by writing to 4 macrocells.
14 The down-counter is clocked by the 8032 ALE signal. When the count reaches zero terminal
15 count, uPSD pin PB4 is pulsed. The 8032 may change the initial counter load value at any
16 time, which chages the divisor of ALE signal as it appears on pin PB4.
17
18 This project was built with Keil PK51, version 7.00, and uses the ISD51 serial
19 debugger on the first UART of uPSD.
20
21 06/2002 Ver 0.1 - Initial Version
22 06/2002 Ver 0.2 - Headerfile fixes
23 06/2002 Ver 0.3 - PWM fixes
24 08/2002 Ver 0.4 - Misc Fixes
25
26 Copyright 2002 ST Microelectronics
27 This example demo code is provided as is and has no warranty,
28 implied or otherwise. You are free to use/modify any of the provided
29 code at your own risk in your applications with the expressed limitation
30 of liability (see below) so long as your product using the code contains
31 at least one uPSD products (device).
32
33 LIMITATION OF LIABILITY: NEITHER STMicroelectronics NOR ITS VENDORS OR
34 AGENTS SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
35 INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
36 CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
37 OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
38 ------------------------------------------------------------------------------*/
39
40 #pragma optimize(8,size)
41 #pragma SYMBOLS
42 #pragma NOAREGS
43
44
45
46 #include "upsd_hardware.h" // environment hardware specific defines
47 #include "upsd3200.h" // special function register declarations for UPSD
48
49 #include "lcd_io.h" // prototype declarations and defines for uPSD IP drivers
50 #include "upsd_timer.h"
51 #include "eeprom.h"
52
53 // Enable one for Uart1 for debug
54 #include "ISD51_U1.h" // Header for ISD51 debugger using uPSD Uart1
55
C51 COMPILER V7.00 DK3200_1_DEMO 01/21/2003 14:51:26 PAGE 2
56 #include <stdlib.h>
57
58 void timer1_init (void);
59 unsigned int timer1_count (void);
60
61 static unsigned int idata timer1_tick;
62 unsigned int timer1_value;
63 BYTE xdata r_stat; // global variable for re-entrancy tests
64
65 //WORD xdata loop_count = 0;
66
67 // test cases
68 enum {
69 e1a,
70 e1b,
71 e1c,
72 e2a,
73 e2b,
74 e2c,
75 e2d,
76 e4a,
77 e4b,
78 e4c,
79 e4d,
80 e4e,
81 e4f,
82 e5a,
83 e6a,
84 e7a,
85 e7b
86 };
87
88
89 xdata PSD_REGS PSD8xx_reg _at_ PSD_REG_ADDR; // Define PSD registers at address "csiop" space
90
91 static void timer1_isr (void) interrupt 3 using 3
92 {
93 1 TR1 = 0; /* stop timer 0 */
94 1
95 1 //printfLCD("T1 Interrupt \n"); //display on LCD
96 1
97 1 // un-comment for read re-entrancy test
98 1 //r_stat = Boot_Flash_Read(SECTOR_0_BASE_ADDRESS);
99 1
100 1 // un-comment for read re-entrancy test
101 1 //r_stat = Boot_Flash_Write(SECTOR_0_BASE_ADDRESS, 0xAA);
102 1
103 1 ET1 = 0; /* enable timer 1 interrupt */
104 1 }
105
106 void timer1_init (void)
107 {
108 1 EA = 0; /* disable interrupts */
109 1 timer1_tick = 0;
110 1 TR1 = 0; /* stop timer 1 */
111 1
112 1 TMOD &= 0xF0; /* clear timer 0 mode bits - bottom 4 bits */
113 1 TMOD |= 0x01; /* put timer 0 into 16-bit no prescale */
114 1
115 1 timer1_value = 0xFFFF;
116 1
117 1 TL1 = (timer1_value & 0x0001);
C51 COMPILER V7.00 DK3200_1_DEMO 01/21/2003 14:51:26 PAGE 3
118 1 TH1 = (timer1_value >> 8);
119 1
120 1 PT1 = 1; /* set high priority for timer 1 */
121 1 ET1 = 0; /* disable timer 1 interrupt */
122 1
123 1 TR1 = 1; /* start timer 1 */
124 1 EA = 1; /* enable interrupts */
125 1 }
126
127 BYTE Sector_Test(BYTE hdr0_status, BYTE hdr1_status)
128 {
129 1 xdata struct sector_header xdata header0;
130 1 xdata struct sector_header xdata header1;
131 1 BYTE idata *ptr;
132 1 BYTE idata i;
133 1 WORD idata address;
134 1 BYTE xdata status;
135 1
136 1 header0.sector_status = hdr0_status;
137 1 header0.sector = SECTOR_0;
138 1 header0.sector_checksum = ~SECTOR_0;
139 1 header0.max_records = 0x0001;
140 1 header0.rec_length = EEPROM_RECORD_SIZE;
141 1 address = SECTOR_0_BASE_ADDRESS;
142 1 ptr = (BYTE*) (&header0);
143 1 for ( i=0; i<sizeof(header0); i++ )
144 1 {
145 2 status = Boot_Flash_Write(address++, ptr[i]);
146 2 }
147 1
148 1 header1.sector_status = hdr1_status;
149 1 header1.sector = SECTOR_1;
150 1 header1.sector_checksum = ~SECTOR_1;
151 1 header1.max_records = 0x0001;
152 1 header1.rec_length = EEPROM_RECORD_SIZE;
153 1 address = SECTOR_1_BASE_ADDRESS;
154 1 ptr = (BYTE*) (&header1);
155 1 for ( i=0; i<sizeof(header1); i++ )
156 1 {
157 2 status = Boot_Flash_Write(address++, ptr[i]);
158 2 }
159 1
160 1 status = Eeprom_Init(); // invalid state - returns INVALID_SECTOR_STATE
161 1
162 1 // status = Eeprom_Sector_Erase(SECTOR_0);
163 1 // status = Eeprom_Sector_Erase(SECTOR_1);
164 1
165 1 return status;
166 1 }
167
168 void main (void) {
169 1
170 1 unsigned int timer2_baud;
171 1 unsigned char status;
172 1 BYTE flag = 1;
173 1 BYTE flag2 = 1;
174 1 BYTE flag3 = 1;
175 1 BYTE flag4 = 1;
176 1 BYTE xdata buf[EEPROM_RECORD_SIZE];
177 1 BYTE xdata buf1[EEPROM_RECORD_SIZE];
178 1 BYTE xdata buf2[EEPROM_RECORD_SIZE];
179 1 BYTE xdata buf3[EEPROM_RECORD_SIZE];
C51 COMPILER V7.00 DK3200_1_DEMO 01/21/2003 14:51:26 PAGE 4
180 1 BYTE xdata buf4[EEPROM_RECORD_SIZE];
181 1 BYTE xdata buftst[1024];
182 1 BYTE xdata buftemp[1024];
183 1 WORD idata i;
184 1 BYTE xdata db;
185 1 BYTE idata e_test;
186 1 // BYTE *ptr;
187 1 WORD xdata loop_count = 0;
188 1
189 1
190 1 // ISD51 makes use of Uart1 or Uart2 based on header file & object file used
191 1
192 1 T2CON = 0x34; // Use Timer 2 as baudrate generator
193 1 // This sets Uart1 to use timer2 baud rate
194 1 PCON |= 0x0C; // Set UART2 to user timer2 baud rate
195 1
196 1 timer2_baud = (65536L - ( (FREQ_OSC * 125L) / (4L * 19200L)));
197 1 RCAP2L = (timer2_baud & 0x00FF);
198 1 RCAP2H = (timer2_baud >> 8);
199 1
200 1 SCON = 0x50; // enable first serial UART & receiver
201 1 SCON2 = 0x50; // enable 2nd uart
202 1 EA = 1; // Enable global interrupt flag
203 1
204 1 PSD8xx_reg.VM |= 0x80; // enable peripheral I/O mode for LCD display
205 1
206 1 timer0_init(); // initialize timer0 interrupt
207 1 timer1_init(); // initialize timer0 interrupt
208 1
209 1 lcd_init(); // initialize LCD. 8 bits, 2 lines, 5x7 font,
210 1 // no blink, cursor off, clear
211 1
212 1 printfLCD("EEPROM Emulation\n"); //display on LCD
213 1 printfLCD("Test\n"); //display on LCD
214 1 delay_2sec();
215 1 lcd_clear();
216 1 // lcd_init(); // initialize LCD. 8 bits, 2 lines, 5x7 font,
217 1
218 1 i = 0;
219 1 status = 0x00;
220 1 for( i=0; i<EEPROM_RECORD_SIZE; i++ )
221 1 {
222 2 buf[i] = 0x11;
223 2 buf1[i] = 0x22;
224 2 buf2[i] = 0x33;
225 2 buf3[i] = 0x44;
226 2 buf4[i] = 0x55;
227 2 }
228 1
229 1 for( i=0; i<1024; i++ )
230 1 {
231 2 buftst[i] = i;
232 2 }
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