upsd_xreg.c

ST公司的upsd34XX评估板固定源程序

// Initialization of uPSD I/Os
//
// William Chin for uPSD3234 from ST Microelectronics
// on June 14, 2002

//-- Includes ----------------------------------------------------------------

#include "general.h"
#include "upsd.h"				// SFRs
#include "upsd_xreg.h"			// extended registers in uPSD

//-- Variables ---------------------------------------------------------------

extern UPSD_xport UPSD_xreg;

//-- Aliases of bit IOs -------------------------------------------------------

//this is just for reference
//#define BELL	UPSD_xreg.DATAOUT_B.bits.PB0

//-- Functions ----------------------------------------------------------------

void initXREG(void) {

   /************ VM ************/
   UPSD_xreg.VM.bits.PIO_EN = 1;          
                                       // bit 7 - PIO (1=enable)
                                       // bit 4 - RD access FLASH (1=enable)
                                       // bit 3 - RD access EEPROM (1=enable)
                                       // bit 2 - PSEN access FLASH (1=enable)
                                       // bit 1 - PSEN access EEPROM (1=enable)
                                       // bit 0 - PSEN access SRAM (1=enable)

   // use port A to genernal I/O port or demuxed lower addresses (a0-a7)
   //UPSD_xreg.DATAOUT_A.byte=0xFF;     // initial output data
   //UPSD_xreg.CONTROL_A.byte=0x03;     // 1=latched address out, 0=genernal I/O
   //UPSD_xreg.DIRECTION_A.byte=0x03;   // 1= ouput mode, 0 = input mode 
   
   // control port A drive characteristic
   //UPSD_xreg.DRIVE_A.byte=0x00;       // upper 4 bits (bit7-4) are for open-drain/CMOS control of PA7-4
                                        // 1 = open drain, 0 = CMOS
                                        // lower 4 bits (bit3-0) are for slew late control of PA3-0
                                        // 1 = higher slew rate, 0 = normal slew rate
 

   // use port B to genernal I/O port or demuxed lower addresses (a0-a7)
   //UPSD_xreg.DATAOUT_B.byte=0xFF;     // initial output data
   //UPSD_xreg.CONTROL_B.byte=0x00;     // 1=latched address out, 0=genernal I/O
   //UPSD_xreg.DIRECTION_B.byte=0xFF;   // 1= ouput mode, 0 = input mode 
   
   // control port B drive characteristic
   //UPSD_xreg.DRIVE_B.byte=0x00;       // upper 4 bits (bit7-4) are for open-drain/CMOS control of PB7-4
                                        // 1 = open drain, 0 = CMOS
                                        // lower 4 bits (bit3-0) are for slew late control of PB3-0
                                        // 1 = higher slew rate, 0 = normal slew rate


   /********* port C ***********/
   // use port C to general I/O port
   //UPSD_xreg.DATAOUT_C.byte=0xFF;     // initial output data
   //UPSD_xreg.DIRECTION_C.byte=0xFF;	// 1= ouput mode, 0 = input mode 

   // control port C drive characteristic
   //UPSD_xreg.DRIVE_C.byte=0x00;		// open-drain/CMOS control of PC7-0
                                        // 1 = open drain, 0 = CMOS


   // use port D to genernal I/O port
   //UPSD_xreg.DATAOUT_D.byte=0x07;		// initial output data
   //UPSD_xreg.DIRECTION_D.byte=0x07;	// 1= ouput mode, 0 = input mode 

   //UPSD_xreg.DRIVE_D.byte=0x07;       // slew rate control of PD2-0
                                        // 1 = higher slew rate, 0 = normal slew rate


   /******* output MCells *******/
   //UPSD_xreg.OMCMASK_AB.byte=0x00;    // write mask control of MCellAB
                                       	// 1 = blocking write, 0 = enable write
   //UPSD_xreg.OMC_AB.byte=0x00;        // write a initial data to Flip-Flops in MCellAB
   
   //UPSD_xreg.OMCMASK_BC.byte=0x00;    // write mask control of MCellBC
                                  		// 1 = blocking write, 0 = enable write
   //UPSD_xreg.OMC_BC.byte=0x00;			// write a initial data to Flip-Flops in MCellBC
                              
   /****** power management ******/
   UPSD_xreg.PMMR0.byte=0x38;            // power-on default = 0x00 
                                        // bit 5 - CLKIN input to MCell (1=off)
                                        // bit 4 - CLKIN input to PLD array (1=off)
                                        // bit 3 - PLD turbo mode (ZPSD only) (1=disable)
                                        // bit 1 - APD unit (1=enable)

   UPSD_xreg.PMMR2.byte=0x70;           // power-on default = 0x00 
                                        // bit 6 - DBE input to PLD array (1=off)
                                        // bit 5 - ALE input to PLD array (1=off)
                                        // bit 4 - CNTL2 input to PLD array (1=off)
                                        // bit 3 - CNTL1 input to PLD array (1=off)
                                        // bit 2 - CNTL0 input to PLD array (1=off)
   /******* JTAG control *******/
   //UPSD_xreg.JTAG.bits.JEN = 1;		// power-on default = 0x00
   										// bit 0 - enable/disable JTAG (1 = enable)
}