📄 upsd_xreg.h
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#ifndef _UPSD_XREG_
#define _UPSD_XREG_
// Modified by William Chin for uPSD3234 from ST Microelectronics
// on June 14, 2002
//******************* New SFRs ************************
//sfr P1SFS = 0x91;
#define bADC0 0x10
#define bADC1 0x20
#define bADC2 0x40
#define bADC3 0x80
//sfr ACON = 0x97;
#define bADEN 0x20
#define bADS1 0x08
#define bADS0 0x04
#define bADST 0x02
#define bADSF 0x01
//sfr IEA = 0xa7;
#define bEDDC 0x80
#define bES2 0x10
#define bEI2C 0x02
#define bEUSB 0x01
//sfr UDT1 = 0xe6;
//sfr UDT0 = 0xe7;
//sfr UISTA = 0xe8;
#define uSUSPENDF 0x80
#define uRSTF 0x20
#define uTXD0F 0x10
#define uRXD0F 0x08
#define uTXD1F 0x04
#define uEOPF 0x02
#define uRESUMEF 0x01
//sfr UIEN = 0xe9;
#define uSUSPNDIE 0x80
#define uTXD0IE 0x10
#define uRXD0IE 0x08
#define uTXD1IE 0x04
#define uEOPIE 0x02
#define uRESUMIE 0x01
//sfr UCON0 = 0xea;
#define uTSEQ0 0x80
#define uSTALL0 0x40
#define uTX0E 0x20
#define uRX0E 0x10
#define uTP0SIZ3 0x08
#define uTP0SIZ2 0x04
#define uTP0SIZ1 0x02
#define uTP0SIZ0 0x01
//sfr UCON1 = 0xeb;
#define uTSEQ1 0x80
#define uEP12SEL 0x40
#define uTX1E 0x20
#define uFRESUM 0x10
#define uTP1SIZ3 0x08
#define uTP1SIZ2 0x04
#define uTP1SIZ1 0x02
#define uTP1SIZ0 0x01
//sfr UCON2 = 0xec;
#define uSOUT 0x10
#define uEP2E 0x08
#define uEP1E 0x04
#define uSTALL2 0x02
#define uSTALL1 0x01
//sfr USTA = 0xed;
#define uRSEQ 0x80
#define uSETUP 0x40
#define uIN 0x20
#define uOUT 0x10
#define uRP0SIZ3 0x08
#define uRP0SIZ2 0x04
#define uRP0SIZ1 0x02
#define uPR0SIZ0 0x01
//sfr UADR = 0xee;
#define uUSBEN 0x80
//sfr UDR0 = 0xef;
//sfr SCON2 = 0x9a;
#define b_TI 0x02
#define b_RI 0x01
#define b_REN 0x10
//sfr SBUF2 = 0x9b;
//sfr WDKEY = 0xae;
#define WD_OFF 0x55
//******************* uPSD xdata register addresses ************************
typedef struct // general structure of 8 bit register allowing bit access
{
unsigned char bit0 : 1;
unsigned char bit1 : 1;
unsigned char bit2 : 1;
unsigned char bit3 : 1;
unsigned char bit4 : 1;
unsigned char bit5 : 1;
unsigned char bit6 : 1;
unsigned char bit7 : 1;
} Register;
typedef union // allow bit or byte access to registers
{
char byte;
Register bits;
} Mix_Reg;
/*
#define DATAIN_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x00))
#define DATAIN_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x01))
#define DATAIN_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x10))
#define DATAIN_D (*(volatile Mix_Reg*)(PSD_REG_BASE+0x11))
#define DATAOUT_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x04))
#define DATAOUT_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x05))
#define DATAOUT_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x12))
#define DATAOUT_D (*(volatile Mix_Reg*)(PSD_REG_BASE+0x13))
#define DIRECTION_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x06))
#define DIRECTION_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x07))
#define DIRECTION_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x14))
#define DIRECTION_D (*(volatile Mix_Reg*)(PSD_REG_BASE+0x15))
#define DRIVE_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x08))
#define DRIVE_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x09))
#define DRIVE_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x16))
#define DRIVE_D (*(volatile Mix_Reg*)(PSD_REG_BASE+0x17))
#define OUTENABLE_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x0C))
#define OUTENABLE_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x0D))
#define OUTENABLE_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x1A))
#define OUTENABLE_D (*(volatile Mix_Reg*)(PSD_REG_BASE+0x1B))
#define CONTROL_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x02))
#define CONTROL_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x03))
#define IMC_A (*(volatile Mix_Reg*)(PSD_REG_BASE+0x0A))
#define IMC_B (*(volatile Mix_Reg*)(PSD_REG_BASE+0x0B))
#define IMC_C (*(volatile Mix_Reg*)(PSD_REG_BASE+0x18))
#define OMC_AB (*(volatile Mix_Reg*)(PSD_REG_BASE+0x20))
#define OMC_BC (*(volatile Mix_Reg*)(PSD_REG_BASE+0x21))
#define OMCMASK_AB (*(Mix_Reg*)(PSD_REG_BASE+0x22))
#define OMCMASK_BC (*(Mix_Reg*)(PSD_REG_BASE+0x23))
#define MAINPROTECT (*(Mix_Reg*)(PSD_REG_BASE+0xC0))
#define ALTPROTECT (*(Mix_Reg*)(PSD_REG_BASE+0xC2))
#define JTAG (*(volatile Mix_Reg*)(PSD_REG_BASE+0xC7))
#define PMMR0 (*(volatile Mix_Reg*)(PSD_REG_BASE+0xB0))
#define PMMR2 (*(volatile Mix_Reg*)(PSD_REG_BASE+0xB4))
#define PAGE (*(volatile Mix_Reg*)(PSD_REG_BASE+0xE0))
#define VM (*(volatile Mix_Reg*)(PSD_REG_BASE+0xE2))
*/
typedef struct {
volatile Mix_Reg DATAIN_A; // PSD_REG_BASE +0x00
volatile Mix_Reg DATAIN_B; // +0x01
volatile Mix_Reg CONTROL_A; // +0x02
volatile Mix_Reg CONTROL_B; // +0x03
volatile Mix_Reg DATAOUT_A; // +0x04
volatile Mix_Reg DATAOUT_B; // +0x05
volatile Mix_Reg DIRECTION_A; // +0x06
volatile Mix_Reg DIRECTION_B; // +0x07
volatile Mix_Reg DRIVE_A; // +0x08
volatile Mix_Reg DRIVE_B; // +0x09
volatile Mix_Reg IMC_A; // +0x0A
volatile Mix_Reg IMC_B; // +0x0B
volatile Mix_Reg OUTENABLE_A; // +0x0C
volatile Mix_Reg OUTENABLE_B; // +0x0D
Mix_Reg res2[2]; // spacer
volatile Mix_Reg DATAIN_C; // +0x10
volatile Mix_Reg DATAIN_D; // +0x11
volatile Mix_Reg DATAOUT_C; // +0x12
volatile Mix_Reg DATAOUT_D; // +0x13
volatile Mix_Reg DIRECTION_C; // +0x14
volatile Mix_Reg DIRECTION_D; // +0x15
volatile Mix_Reg DRIVE_C; // +0x16
volatile Mix_Reg DRIVE_D; // +0x17
volatile Mix_Reg IMC_C; // +0x18
Mix_Reg res1a; // spacer
volatile Mix_Reg OUTENABLE_C; // +0x1A
volatile Mix_Reg OUTENABLE_D; // +0x1B
Mix_Reg res4[4]; // spacer
volatile Mix_Reg OMC_AB; // +0x20
volatile Mix_Reg OMC_BC; // +0x21
volatile Mix_Reg OMCMASK_AB; // +0x22
volatile Mix_Reg OMCMASK_BC; // +0x23
Mix_Reg res8c[0x8C]; // spacer
volatile Mix_Reg PMMR0; // +0xB0
Mix_Reg res1b; // spacer
volatile Mix_Reg PMMR1; // +0xB2
Mix_Reg res1c; // spacer
volatile Mix_Reg PMMR2; // +0xB4
Mix_Reg res0B[0x0B]; // spacer
volatile Mix_Reg MAINPROTECT; // +0xC0
Mix_Reg res1d; // spacer
volatile Mix_Reg ALTPROTECT; // +0xC2
Mix_Reg res4a[4]; // spacer
volatile Mix_Reg JTAG; // +0xC7
Mix_Reg res18[0x18]; // spacer
volatile Mix_Reg PAGE; // +0xE0
Mix_Reg res1e; // spacer
volatile Mix_Reg VM; // +0xE2
Mix_Reg res29[0x1d]; // spacer
} UPSD_xport;
//****************** uPSD control register bit definitions *********
//PSD PORTA
#define PA0 bit0
#define PA1 bit1
#define PA2 bit2
#define PA3 bit3
#define PA4 bit4
#define PA5 bit5
#define PA6 bit6
#define PA7 bit7
//PSD PORTB
#define PB0 bit0
#define PB1 bit1
#define PB2 bit2
#define PB3 bit3
#define PB4 bit4
#define PB5 bit5
#define PB6 bit6
#define PB7 bit7
//PSD PORTC
#define PC0 bit0
#define PC1 bit1
#define PC2 bit2
#define PC3 bit3
#define PC4 bit4
#define PC5 bit5
#define PC6 bit6
#define PC7 bit7
//PSD PORTD
#define PD0 bit0
#define PD1 bit1
#define PD2 bit2
//PSD JTAG
#define JEN bit0 // JTAG enable
//PSD PMMR0
#define APD_ENABLE bit1
#define PLD_TURBO bit3
#define PLD_ARRAY_CLK bit4
#define PLD_MCELL_CLK bit5
//PSD PMMR2
#define PLD_CNTL0 bit2
#define PLD_CNTL1 bit3
#define PLD_CNTL2 bit4
#define PLD_ALE bit5
#define PLD_DBE bit6
//PSD VM
#define SRAM_CODE bit0
#define EE_CODE bit1
#define FL_CODE bit2
#define EE_DATA bit3
#define FL_DATA bit4
#define PIO_EN bit7
//****************** Flash parameters ******************
#define NVM_DATA_POLL 0x80 // flash status "data poll" bit at DQ7
#define NVM_DATA_TOGGLE 0x40 // flash status "toggle poll" bit at DQ6
#define NVM_ERROR 0x20 // flash status "error" bit at DQ5
#endif
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