upsd_xreg.lst

ST公司的upsd34XX评估板固定源程序

C51 COMPILER V7.06   UPSD_XREG                                                             10/10/2004 20:51:48 PAGE 1   


C51 COMPILER V7.06, COMPILATION OF MODULE UPSD_XREG
OBJECT MODULE PLACED IN upsd_xreg.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE upsd_xreg.c LARGE BROWSE DEBUG OBJECTEXTEND

stmt level    source

   1          // Initialization of uPSD I/Os
   2          //
   3          // William Chin for uPSD3234 from ST Microelectronics
   4          // on June 14, 2002
   5          
   6          //-- Includes ----------------------------------------------------------------
   7          
   8          #include "general.h"
   9          #include "upsd.h"                               // SFRs
  10          #include "upsd_xreg.h"                  // extended registers in uPSD
  11          
  12          //-- Variables ---------------------------------------------------------------
  13          
  14          extern UPSD_xport UPSD_xreg;
  15          
  16          //-- Aliases of bit IOs -------------------------------------------------------
  17          
  18          //this is just for reference
  19          //#define BELL  UPSD_xreg.DATAOUT_B.bits.PB0
  20          
  21          //-- Functions ----------------------------------------------------------------
  22          
  23          void initXREG(void) {
  24   1      
  25   1         /************ VM ************/
  26   1         UPSD_xreg.VM.bits.PIO_EN = 1;          
  27   1                                             // bit 7 - PIO (1=enable)
  28   1                                             // bit 4 - RD access FLASH (1=enable)
  29   1                                             // bit 3 - RD access EEPROM (1=enable)
  30   1                                             // bit 2 - PSEN access FLASH (1=enable)
  31   1                                             // bit 1 - PSEN access EEPROM (1=enable)
  32   1                                             // bit 0 - PSEN access SRAM (1=enable)
  33   1      
  34   1         // use port A to genernal I/O port or demuxed lower addresses (a0-a7)
  35   1         //UPSD_xreg.DATAOUT_A.byte=0xFF;     // initial output data
  36   1         //UPSD_xreg.CONTROL_A.byte=0x03;     // 1=latched address out, 0=genernal I/O
  37   1         //UPSD_xreg.DIRECTION_A.byte=0x03;   // 1= ouput mode, 0 = input mode 
  38   1         
  39   1         // control port A drive characteristic
  40   1         //UPSD_xreg.DRIVE_A.byte=0x00;       // upper 4 bits (bit7-4) are for open-drain/CMOS control of PA7-4
  41   1                                              // 1 = open drain, 0 = CMOS
  42   1                                              // lower 4 bits (bit3-0) are for slew late control of PA3-0
  43   1                                              // 1 = higher slew rate, 0 = normal slew rate
  44   1       
  45   1      
  46   1         // use port B to genernal I/O port or demuxed lower addresses (a0-a7)
  47   1         //UPSD_xreg.DATAOUT_B.byte=0xFF;     // initial output data
  48   1         //UPSD_xreg.CONTROL_B.byte=0x00;     // 1=latched address out, 0=genernal I/O
  49   1         //UPSD_xreg.DIRECTION_B.byte=0xFF;   // 1= ouput mode, 0 = input mode 
  50   1         
  51   1         // control port B drive characteristic
  52   1         //UPSD_xreg.DRIVE_B.byte=0x00;       // upper 4 bits (bit7-4) are for open-drain/CMOS control of PB7-4
  53   1                                              // 1 = open drain, 0 = CMOS
  54   1                                              // lower 4 bits (bit3-0) are for slew late control of PB3-0
  55   1                                              // 1 = higher slew rate, 0 = normal slew rate
C51 COMPILER V7.06   UPSD_XREG                                                             10/10/2004 20:51:48 PAGE 2   

  56   1      
  57   1      
  58   1         /********* port C ***********/
  59   1         // use port C to general I/O port
  60   1         //UPSD_xreg.DATAOUT_C.byte=0xFF;     // initial output data
  61   1         //UPSD_xreg.DIRECTION_C.byte=0xFF;   // 1= ouput mode, 0 = input mode 
  62   1      
  63   1         // control port C drive characteristic
  64   1         //UPSD_xreg.DRIVE_C.byte=0x00;               // open-drain/CMOS control of PC7-0
  65   1                                              // 1 = open drain, 0 = CMOS
  66   1      
  67   1      
  68   1         // use port D to genernal I/O port
  69   1         //UPSD_xreg.DATAOUT_D.byte=0x07;             // initial output data
  70   1         //UPSD_xreg.DIRECTION_D.byte=0x07;   // 1= ouput mode, 0 = input mode 
  71   1      
  72   1         //UPSD_xreg.DRIVE_D.byte=0x07;       // slew rate control of PD2-0
  73   1                                              // 1 = higher slew rate, 0 = normal slew rate
  74   1      
  75   1      
  76   1         /******* output MCells *******/
  77   1         //UPSD_xreg.OMCMASK_AB.byte=0x00;    // write mask control of MCellAB
  78   1                                              // 1 = blocking write, 0 = enable write
  79   1         //UPSD_xreg.OMC_AB.byte=0x00;        // write a initial data to Flip-Flops in MCellAB
  80   1         
  81   1         //UPSD_xreg.OMCMASK_BC.byte=0x00;    // write mask control of MCellBC
  82   1                                                      // 1 = blocking write, 0 = enable write
  83   1         //UPSD_xreg.OMC_BC.byte=0x00;                        // write a initial data to Flip-Flops in MCellBC
  84   1                                    
  85   1         /****** power management ******/
  86   1         UPSD_xreg.PMMR0.byte=0x38;            // power-on default = 0x00 
  87   1                                              // bit 5 - CLKIN input to MCell (1=off)
  88   1                                              // bit 4 - CLKIN input to PLD array (1=off)
  89   1                                              // bit 3 - PLD turbo mode (ZPSD only) (1=disable)
  90   1                                              // bit 1 - APD unit (1=enable)
  91   1      
  92   1         UPSD_xreg.PMMR2.byte=0x70;           // power-on default = 0x00 
  93   1                                              // bit 6 - DBE input to PLD array (1=off)
  94   1                                              // bit 5 - ALE input to PLD array (1=off)
  95   1                                              // bit 4 - CNTL2 input to PLD array (1=off)
  96   1                                              // bit 3 - CNTL1 input to PLD array (1=off)
  97   1                                              // bit 2 - CNTL0 input to PLD array (1=off)
  98   1         /******* JTAG control *******/
  99   1         //UPSD_xreg.JTAG.bits.JEN = 1;               // power-on default = 0x00
 100   1                                                                                      // bit 0 - enable/disable JTAG (1 = enable)
 101   1      }
 102          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =     20    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)