📄 main.c
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/*********************************************************************
* Filename: main.c *
* *
* Author: Aming, Maglev Reserch Center of NUDT. *
* *
* Last Modified: 06/30/04 *
* *
* Description: Main program file for TMS320LF2407A DSP. *
*********************************************************************/
#include "2407reg.h"
#include "main.h"
#include "util.h"
unsigned int iope0;
unsigned int xf;
unsigned int can_err;
unsigned int can_txdata[4];
unsigned int can_rxdata[4];
unsigned int counter;
void main(void)
{
unsigned int i=0;
unsigned char s;
initcpu();
iope0 = 0;
xf = 0;
counter = 0;
kickdog();
while(1){
if (counter >= 2000 && counter <= 4000 && !(*PEDATDIR & 0x0001)){
*PEDATDIR |= 0x0001;
}
else if (counter >= 4000){
counter = 0;
*PEDATDIR &= 0xfffe;
}
kickdog();
}
}
interrupt void int1()
{
}
interrupt void int2()
{
unsigned int can_ifr;
*EVAIFRA |= 0x0002;
counter++;
}
interrupt void int3()
{
*IFR = 0x04;
*EVAIFRB |= 0x0001;
if (iope0 == 0){
*PEDATDIR |= 0x0001;
iope0 = 1;
}
else{
*PEDATDIR &= 0xfffe;
iope0 = 0;
}
}
interrupt void int4()
{
}
interrupt void int5()
{
unsigned int pivr;
unsigned int can_ifr;
pivr = *PIVR;
*IFR = 0x10;
switch (pivr){
case 0x40:
*PIACKR1 = *PIACKR1 & 0x0400;
can_ifr = *CANIFR;
if (can_ifr & 0x2000){
*CANTCR |= 0x8000;
}
if (can_ifr & 0x0100){
can_rx(can_rxdata);
}
break;
case 0x41:
*PIACKR1 = *PIACKR1 & 0x0800;
can_ifr = *CANIFR;
can_err = can_ifr & 0xff;
break;
default:
break;
}
}
interrupt void int6()
{
}
interrupt void phantom()
{
/*Do nothing*/
}
void initcpu()
{
disable();
/*** Configure the System Control and Status registers ***/
*SYSCR1 = 0x00fd;
/*
bit 15 0: reserved
bit 14 0: CLKOUT = CPUCLK
bit 13¨C12 00: IDLE1 selected for low¨Cpower mode
bit 11¨C9 000: PLL x4 mode
bit 8 0: reserved
bit 7 1: 1 = enable ADC module clock
bit 6 1: 1 = enable SCI module clock
bit 5 1: 1 = enable SPI module clock
bit 4 1: 1 = enable CAN module clock
bit 3 1: 1 = enable EVB module clock
bit 2 1: 1 = enable EVA module clock
bit 1 0: reserved
bit 0 0: clear the ILLADR bit
*/
*SYSCR2 = (*SYSCR2 & 0x04) | 0x0a;
/*
bit 15¨C6 0 0's: reserved
bit 5 0: do NOT clear the WD OVERRIDE bit
bit 4 0: XMIF_HI¨CZ, 0=normal mode, 1=Hi¨CZ'd
bit 3 1: disable the boot ROM, enable the FLASH
bit 2 no change MP/MC* bit reflects state of MP/MC* pin
bit 1¨C0 10: 10 = SARAM mapped to data
*/
/*** Disable the watchdog timer ***/
*WDCR = 0x0068;
/*
bits 15¨C8 0's: reserved
bit 7 1: clear WD flag
bit 6 1: disable the dog
bit 5¨C3 101: must be written as 101
bit 2¨C0 000: WDCLK divider = 1
*/
/*** Setup external memory interface for LF2407 EVM ***/
WSGR = 0x0048;
/*
bit 15¨C11 0's: reserved
bit 10¨C9 00: bus visibility off
bit 8¨C6 001: 1 wait¨Cstate for I/O space
bit 5¨C3 001: 1 wait¨Cstate for data space
bit 2¨C0 000: 0 wait state for program space
*/
/*** Setup shared I/O pins ***/
*MCRA = 0x0040; /* group A pins */
/*
bit 15 0: 0=IOPB7, 1=TCLKINA
bit 14 0: 0=IOPB6, 1=TDIRA
bit 13 0: 0=IOPB5, 1=T2PWM/T2CMP
bit 12 0: 0=IOPB4, 1=T1PWM/T1CMP
bit 11 0: 0=IOPB3, 1=PWM6
bit 10 0: 0=IOPB2, 1=PWM5
bit 9 0: 0=IOPB1, 1=PWM4
bit 8 0: 0=IOPB0, 1=PWM3
bit 7 0: 0=IOPA7, 1=PWM2
bit 6 1: 0=IOPA6, 1=PWM1
bit 5 0: 0=IOPA5, 1=CAP3
bit 4 0: 0=IOPA4, 1=CAP2/QEP2
bit 3 0: 0=IOPA3, 1=CAP1/QEP1
bit 2 0: 0=IOPA2, 1=XINT1
bit 1 0: 0=IOPA1, 1=SCIRXD
bit 0 0: 0=IOPA0, 1=SCITXD
*/
*MCRB = 0xFEC0; /* group B pins */
/*
bit 15 1: 0=reserved, 1=TMS2 (always write as 1)
bit 14 1: 0=reserved, 1=TMS (always write as 1)
bit 13 1: 0=reserved, 1=TD0 (always write as 1)
bit 12 1: 0=reserved, 1=TDI (always write as 1)
bit 11 1: 0=reserved, 1=TCK (always write as 1)
bit 10 1: 0=reserved, 1=EMU1 (always write as 1)
bit 9 1: 0=reserved, 1=EMU0 (always write as 1)
bit 8 0: 0=IOPD0, 1=XINT2/ADCSOC
bit 7 1: 0=IOPC7, 1=CANRX
bit 6 1: 0=IOPC6, 1=CANTX
bit 5 0: 0=IOPC5, 1=SPISTE
bit 4 0: 0=IOPC4, 1=SPICLK
bit 3 0: 0=IOPC3, 1=SPISOMI
bit 2 0: 0=IOPC2, 1=SPISIMO
bit 1 0: 0=IOPC1, 1=BIO*
bit 0 0: 0=IOPC0, 1=W/R*
*/
*MCRC = 0x0000; /* group C pins */
/*
bit 15 0: reserved
bit 14 0: 0=IOPF6, 1=IOPF6
bit 13 0: 0=IOPF5, 1=TCLKINB
bit 12 0: 0=IOPF4, 1=TDIRB
bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP
bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP
bit 9 0: 0=IOPF1, 1=CAP6
bit 8 0: 0=IOPF0, 1=CAP5/QEP4
bit 7 0: 0=IOPE7, 1=CAP4/QEP3
bit 6 0: 0=IOPE6, 1=PWM12
bit 5 0: 0=IOPE5, 1=PWM11
bit 4 0: 0=IOPE4, 1=PWM10
bit 3 0: 0=IOPE3, 1=PWM9
bit 2 0: 0=IOPE2, 1=PWM8
bit 1 0: 0=IOPE1, 1=PWM7
bit 0 0: 0=IOPE0, 1=CLKOUT
*/
/*** Configure IOPE0 pin as an output ***/
*PEDATDIR = *PEDATDIR | 0x0100;
/*** Setup timers 1 and 2, and the PWM configuration ***/
*T1CON = 0x0000; /* disable timer 1 */
*T2CON = 0x0000; /* disable timer 2 */
*GPTCONA = 0x0000; /* configure GPTCONA */
/*
bit 15 0: reserved
bit 14 0: T2STAT, read¨Conly
bit 13 0: T1STAT, read¨Conly
bit 12¨C11 00: reserved
bit 10¨C9 00: T2TOADC, 00 = no timer2 event starts ADC
bit 8¨C7 00: T1TOADC, 00 = no timer1 event starts ADC
bit 6 0: TCOMPOE, 0 = Hi¨Cz all timer compare outputs
bit 5¨C4 00: reserved
bit 3¨C2 00: T2PIN, 00 = forced low
bit 1¨C0 00: T1PIN, 00 = forced low
*/
/* Timer 1: configure to clock the PWM on PWM1 pin */
/* Symmetric PWM, 10KHz carrier frequency, 25% duty cycle */
*T1CNT = 0x0000; /* clear timer counter */
*T1PR = 10000; /* set timer period */
*DBTCONA = 0x0000; /* deadband units off */
*CMPR1 = 0; /* set PWM1 duty cycle */
*ACTRA = 0x0002; /* PWM1 pin set active high */
/*
bit 15 0: space vector dir is CCW (don't care)
bit 14¨C12 000: basic space vector is 000 (dont' care)
bit 11¨C10 00: PWM6/IOPB3 pin forced low
bit 9¨C8 00: PWM5/IOPB2 pin forced low
bit 7¨C6 00: PWM4/IOPB1 pin forced low
bit 5¨C4 00: PWM3/IOPB0 pin forced low
bit 3¨C2 00: PWM2/IOPA7 pin forced low
bit 1¨C0 10: PWM1/IOPA6 pin active high
*/
*COMCONA = 0x8200; /* configure COMCON register */
/*
bit 15 1: 1 = enable compare operation
bit 14¨C13 00: 00 = reload CMPRx regs on timer 1 underflow
bit 12 0: 0 = space vector disabled
bit 11¨C10 00: 00 = reload ACTR on timer 1 underflow
bit 9 1: 1 = enable PWM pins
bit 8¨C0 0's: reserved
*/
*T1CON = 0x1040; /* configure T1CON register */
/*
bit 15¨C14 00: stop immediately on emulator suspend
bit 13 0: reserved
bit 12¨C11 01: 01 = continous¨Cup/down count mode
bit 10¨C8 000: 000 = x/1 prescaler
bit 7 0: reserved in T1CON
bit 6 1: TENABLE, 1 = enable timer
bit 5¨C4 00: 00 = CPUCLK is clock source
bit 3¨C2 00: 00 = reload compare reg on underflow
bit 1 0: 0 = disable timer compare
bit 0 0: reserved in T1CON
*/
/* Timer 2: configure to generate a 100ms periodic interrupt */
*T2CNT = 0x0000; /* clear timer counter */
*T2PR = 31250; /* set timer period */
*T2CON = 0xd740; /* configure T2CON register */
/*
bit 15¨C14 11: stop immediately on emulator suspend
bit 13 0: reserved
bit 12¨C11 10: 10 = continous¨Cup count mode
bit 10¨C8 111: 111 = x/128 prescaler
bit 7 0: T2SWT1, 0 = use own TENABLE bit
bit 6 1: TENABLE, 1 = enable timer
bit 5¨C4 00: 00 = CPUCLK is clock source
bit 3¨C2 00: 00 = reload compare reg on underflow
bit 1 0: 0 = disable timer compare
bit 0 0: SELT1PR, 0 = use own period register
*/
/*** Setup the core interrupts ***/
*IMR = 0x0000; /* clear the IMR register */
*IFR = 0x003F; /* clear any pending core interrupts */
*IMR = 0x0002; /* enable desired core interrupts */
/*** Setup the event manager interrupts ***/
*EVAIFRA = 0xFFFF; /* clear all EVA group A interrupts */
*EVAIFRB = 0xFFFF; /* clear all EVA group B interrupts */
*EVAIFRC = 0xFFFF; /* clear all EVA group C interrupts */
*EVAIMRA = 0x0002; /* enable desired EVA group A interrupts */
*EVAIMRB = 0x0001; /* enable desired EVA group B interrupts */
*EVAIMRC = 0x0000; /* enable desired EVA group C interrupts */
*EVBIFRA = 0xFFFF; /* clear all EVB group A interrupts */
*EVBIFRB = 0xFFFF; /* clear all EVB group B interrupts */
*EVBIFRC = 0xFFFF; /* clear all EVB group C interrupts */
*EVBIMRA = 0x0000; /* enable desired EVB group A interrupts */
*EVBIMRB = 0x0000; /* enable desired EVB group B interrupts */
*EVBIMRC = 0x0000; /* enable desired EVB group C interrupts */
/*SYSCR2=*SYSCR2&0xfffc|0x02; */
asm(" CLRC SXM"); /*Clear Sign Extension Mode*/
asm(" CLRC CNF"); /*Config Block B0 for data mem*/
asm(" CLRC OVM"); /*Reset Overflow Mode*/
asm(" CLRC XF");
kickdog(); /*Reset watchdog*/
init_can();
init_sci(2000000);
enable();
}
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