📄 cstartup.s
字号:
#;------------------------------------------------------------------------------
#;- ATMEL Microcontroller Software Support - ROUSSET -
#;------------------------------------------------------------------------------
#; The software is delivered "AS IS" without warranty or condition of any
#; kind, either express, implied or statutory. This includes without
#; limitation any warranty or condition with respect to merchantability or
#; fitness for any particular purpose, or against the infringements of
#; intellectual property rights of others.
#;-----------------------------------------------------------------------------
#;- File source : cstartup_ice.s
#;- Object : Boot for simulate Final Application version to be
#;- loaded in SRAM. Only change as the internal RAM address
#;- and support the Semihosting
#;- Compilation flag : SEMIHOSTING => use the semihosting facilities
#;-
#;- 1.0 06/04/00 JPP : Creation
#;- 1.1 18/08/00 JCZ : Over-comment and optimize
#;- 1.2 25/10/00 JPP : Global for including
#;------------------------------------------------------------------------------
#; .INCLUDE "targets/eb40/eb40.inc"
.INCLUDE "periph/aic/aic.inc"
.INCLUDE "periph/arm7tdmi/arm.inc"
.INCLUDE "periph/special_function/sf.inc"
.INCLUDE "periph/ebi/ebi.inc"
.INCLUDE "periph/power_saving/apmc55800.inc"
.IFDEF AT91_DEBUG_ICE
.EQU RAM_BASE, 0x0000000 /* internal Ram base address after remap */
.ELSE
.EQU RAM_BASE, 0x0300000 /* internal Ram base address before remap */
.ENDIF
.EQU FLASH_BASE, 0x01000000
.EQU EXT_SRAM_BASE, 0x02000000
.EQU EXT_SRAM_SIZE, (512*1024) /* 512 Kbytes */
.EQU EXT_SRAM_LIMIT, (EXT_SRAM_BASE+EXT_SRAM_SIZE)
#;------------------------------------------------------------------------------
#;- EBI Initialization Data
#;-------------------------
#;- The EBI User Interface Image which is copied by the boot.
#;- 32,768MHz master clock assumed.
#;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
#;- EBI Base Address is added at the end for commodity in copy code.
#;------------------------------------------------------------------------------
.EQU EBI_CSR_0, (FLASH_BASE | 0x2529) /* 0x01000000, 16MB, 2 tdf, 16 bits, 2 WS */
.EQU EBI_CSR_1, (EXT_SRAM_BASE | 0x2121) /* 0x02000000, 16MB, 0 hold, 16 bits, 1 WS */
.EQU EBI_CSR_2, 0x20000000 /* unused */
.EQU EBI_CSR_3, 0x30000000 /* unused */
.EQU EBI_CSR_4, 0x40000000 /* unused */
.EQU EBI_CSR_5, 0x50000000 /* unused */
.EQU EBI_CSR_6, 0x60000000 /* unused */
.EQU EBI_CSR_7, 0x70000000 /* unused */
#;------------------------------------------------------------------------------
#;- Area Definition
#;-----------------
#;- Must be defined as function to put first in the code as it must be mapped
#;- at SRAM.
#;------------------------------------------------------------------------------
# AREA reset, CODE, READONLY, INTERWORK
#;------------------------------------------------------------------------------
#;- Semihosting support
#;--------------------------------
#;- The C runtime library is the IO functions provided by the semihosting.
#;- They are generally costly in code and can be used as the debugger mode (ICE)
#;------------------------------------------------------------------------------
#;- Define "__main" to ensure that C runtime system is not linked
.global __main
__main:
#;------------------------------------------------------------------------------
#;- Define the entry point
#;------------------------
#;- Note on the link address and the Remap command.
#;- In order to guarantee that the non position-independant code (the ARM linker
#;- armlink doesn't generate position-independant code) can work on the ARM,
#;- it must be linked at address at which it expects to run.
#;- In this startup example, we use RAM as base address.
#;------------------------------------------------------------------------------
# ENTRY
__entry:
#;------------------------------------------------------------------------------
#;- Exception vectors
#;--------------------
#;- In the ICE function your board as run the boot code and initialize the remap
#;- feature. but these code it's location independant and can be emulate the csartup_fash
#;- fonctionnality.
#;- These vectors are read at RAM address. in Flash mode these vectors are at 0
#;- They absolutely requires to be in relative addresssing mode in order to
#;- guarantee a valid jump. For the moment, all are just looping (what may be
#;- dangerous in a final system). If an exception occurs before remap, this
#;- would result in an infinite loop.
#;------------------------------------------------------------------------------
B InitReset /* reset */
undefvec:
B undefvec /* Undefined Instruction */
swivec:
B swivec /* Software Interrupt */
pabtvec:
B pabtvec /* Prefetch Abort */
dabtvec:
B dabtvec /* Data Abort */
rsvdvec:
B rsvdvec /* reserved */
irqvec:
B irqvec /* reserved */
fiqvec:
B fiqvec /* reserved */
#;------------------------------------------------------------------------------
#;- Exception vectors ( after cstartup execution )
#;------------------------------------
#;- These vectors are read at RAM address after the remap command is performed in
#;- the EBI. As they will be relocated at address 0x0 to be effective, a
#;- relative addressing is forbidden. The only possibility to get an absolute
#;- addressing for an ARM vector is to read a PC relative value at a defined
#;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
#;- vectors) for storing the absolute exception handler address.
#;- The AIC vectoring access vectors are saved in the interrupt and fast
#;- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
#;- offset is never used).
#;- The provisory handler addresses are defined on infinite loop and can be
#;- modified at any time.
#;- Note also that the reset is only accessible by a jump from the application
#;- to 0. It is an actual software reset.
#;- As the 13 first location are used by the vectors, the read/write link
#;- address must be defined from 0x34 if internal data mapping is required.
#;- (use for that the option -rw- base=0x34
#;------------------------------------------------------------------------------
VectorTable:
ldr pc, [pc, #+0x18] /* SoftReset */
ldr pc, [pc, #+0x18] /* UndefHandler */
ldr pc, [pc, #+0x18] /* SWIHandler */
ldr pc, [pc, #+0x18] /* PrefetchAbortHandler */
ldr pc, [pc, #+0x18] /* DataAbortHandler */
nop /* Reserved */
ldr pc, [pc,#-0xF20] /* IRQ : read the AIC */
ldr pc, [pc,#-0xF20] /* FIQ : read the AIC */
#;- There are only 5 offsets as the vectoring is used.
.long SoftReset
.long UndefHandler
.long SWIHandler
.long PrefetchAbortHandler
.long DataAbortHandler
#;- Vectoring Execution function run at absolut addresss
SoftReset:
b SoftReset
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PrefetchAbortHandler:
b PrefetchAbortHandler
#; Return at the next THUMB address after the data abort
DataAbortHandler:
.extern data_abort
add R12,R14,#-5 /* Return address to THUMB after data abort */
LDR R11,=data_abort /* Set the data abort Flag */
STR R12,[R11]
msr CPSR_c, #ARM_MODE_USER /* set User mode */
bx R12 /* branch in THUMB */
#;------------------------------------------------------------------------------
#;- EBI Initialization Data
#;-------------------------
#;- The EBI values depend to target choice , Clock, and memories access time.
#;- Yous must be define these values in include file
#;- The EBI User Interface Image which is copied by the boot.
#;- The EBI_CSR_x are defined in the target and hardware depend.
#;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
#;- EBI Base Address is added at the end for commodity in copy code.
#;- ICE note :For ICE debug no need to set the EBI value these values already set
#;- by the boot function.
#;------------------------------------------------------------------------------
InitTableEBI:
.long EBI_CSR_0
.long EBI_CSR_1
.long EBI_CSR_2
.long EBI_CSR_3
.long EBI_CSR_4
.long EBI_CSR_5
.long EBI_CSR_6
.long EBI_CSR_7
.long 0x00000001 /* REMAP command */
.long 0x00000006 /* 6 memory regions, standard read */
PtEBIBase:
.long EBI_BASE /* EBI Base Address */
#;------------------------------------------------------------------------------
#;- The reset handler before Remap
#;--------------------------------
#;- From here, the code is executed from SRAM address
#;------------------------------------------------------------------------------
InitReset:
#;------------------------------------------------------------------------------
#;- Speed up the Boot sequence
#;----------------------------
#;- After reset, the number os wait states on chip select 0 is 8. All AT91
#;- Evaluation Boards fits fast flash memories, so that the number of wait
#;- states can be optimized to fast up the boot sequence.
#;- ICE note :For ICE debug no need to set the EBI value these values already set
#;- by the boot function.
#;------------------------------------------------------------------------------
#;- Load System EBI Base address and CSR0 Init Value
ldr r0, PtEBIBase
ldr r1, [pc,#-(8+.-InitTableEBI)] /* values (relative) */
#;- Speed up code execution by disabling wait state on Chip Select 0
str r1, [r0]
#;------------------------------------------------------------------------------
#;- low level init
#;----------------
#; Call __low_level_init to perform initialization before initializing
#; AIC and calling main.
#;----------------------------------------------------------------------
ldr r2, =SF_BASE /* Get the SF_BASE.SF_CIDR */
ldr r2, [R2,#SF_CIDR]
ldr r1, =SF_ARCH /* Get Architecture Mask */
and r1,R1,R2 /* Get the Internal Ram size */
ldr R2, =SF_ARCH_AT91x55
cmp R1,R2
.IFDEF AT91_DEBUG_ICE
.ELSE
bleq __low_level_init
.ENDIF
#;------------------------------------------------------------------------------
#;- Reset the Interrupt Controller
#;--------------------------------
#;- Normally, the code is executed only if a reset has been actually performed.
#;- So, the AIC initialization resumes at setting up the default vectors.
#;------------------------------------------------------------------------------
#;- Load the AIC Base Address and the default handler addresses
add r0, pc,#-(8+.-AicData) /* @ where to read values (relative) */
ldmia r0, {r1-r4}
#;- Setup the Spurious Vector
str r4, [r1, #AIC_SPU] /* r4 = spurious handler */
#;- ICE note : For ICE debug
#;- Perform 8 End Of Interrupt Command to make sure AIC will not lock out nIRQ
mov r0, #8
LoopAic0:
str r1, [r1, #AIC_EOICR] /* any value written */
subs r0, r0, #1
bhi LoopAic0
#;- Set up the default interrupt handler vectors
str r2, [r1, #AIC_SVR] /* SVR[0] for FIQ */
add r1, r1, #AIC_SVR
mov r0, #31 /* counter */
LoopAic1:
str r3, [r1, r0, LSL #2] /* SVRs for IRQs */
subs r0, r0, #1 /* do not save FIQ */
bhi LoopAic1
b EndInitAic
#;- Default Interrupt Handlers
AicData:
.long AIC_BASE /* AIC Base Address */
#;------------------------------------------------------------------------------
#;- Default Interrupt Handler
#;---------------------------
#;- These function are defined in the AT91 library. If you want to change this
#;- you can redifine these function in your appication code
#;------------------------------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -