half_1.vhd

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--block------
--***************************
library ieee;
use ieee.std_logic_1164.all;   --库定义                                 
--*************************--
ENTITY half_1 IS
  PORT(a,b: in bit;
        s,c:out bit);
END  ;                             --端口定义     
--************************************
ARCHITECTURE addr1 OF half_1  IS
BEGIN
   s<=a xor b;
   c<=a and b;
end addr1;
ARCHITECTURE addr2 OF half_1  IS
BEGIN
  example:block
     PORT(a,b: in bit;
        s,c:out bit);
    port map(a,b,s,c);
  begin
   p1:process(a,b)
    begin
      s<=a or b;
   end process p1;
   p2:process(a,b)
    begin
      c<=a and b;
    end process p2;
   end block example;
 end addr2;


configuration and2xor of half_1 is
for addr2
end for;
end and2xor;