📄 latch.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity latch is
port(d,clk: in bit;
q,qb: out bit);
end latch;
architecture latch_guard of latch is
begin
g1:
block (clk='1')
begin
q<=guarded d after 5 ns;
qb<=guarded not(d) after 7 ns;
end block g1;
end latch_guard;
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