divp98.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY divp98 IS
		PORT(reset: IN std_logic;
             clk_input:in  std_logic;
               clk_2 :out  std_logic;
               clk_4 :out  std_logic);
     END divp98;
-----------------------------
ARCHITECTURE beh OF divp98 IS
 signal count:  std_logic_vector(1 downto 0);
 BEGIN 
    PROCESS(reset,clk_input)
     BEGIN
       IF(reset='0')THEN
          count(1 downto 0)<="00";
          else
         if (clk_input'event and clk_input='1')then
             count(1 downto 0)<=count(1 downto 0)+1;
           else
             null;
             end if;
           end if;
       end process;
     clk_2<=count(0);
     clk_4<=count(1);
  end beh;