📄 and2_3.vhd
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--与非门行为描述:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2_3 IS
PORT(
a,b: IN bit;
y: OUT bit);
END ;
ARCHITECTURE behav OF and2_3 IS
begin
process(a,b)
variable tmp: bit_vector(1 downto 0);
begin
tmp:=a&b;
case tmp is
when"00"=>y<='1';
when"01"=>y<='1';
when"10"=>y<='1';
when"11"=>y<='0';
end case;
end process;
end behav;
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