📄 ex6.rpt
字号:
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl_ex\ex6.rpt
ex6
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 23 B DFFE + t 0 0 0 2 1 7 4 |74160:10|QA (|74160:10|:6)
- 18 B TFFE + t 0 0 0 2 3 7 3 |74160:10|QB (|74160:10|:7)
- 20 B TFFE + t 0 0 0 2 3 7 2 |74160:10|QC (|74160:10|:8)
- 22 B DFFE + t 0 0 0 2 4 7 2 |74160:10|QD (|74160:10|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl_ex\ex6.rpt
ex6
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC17 A0
| +------------------- LC19 A1
| | +----------------- LC21 A2
| | | +--------------- LC24 A3
| | | | +------------- LC25 A4
| | | | | +----------- LC27 A5
| | | | | | +--------- LC29 A6
| | | | | | | +------- LC23 |74160:10|QA
| | | | | | | | +----- LC18 |74160:10|QB
| | | | | | | | | +--- LC20 |74160:10|QC
| | | | | | | | | | +- LC22 |74160:10|QD
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC23 -> * * * * * * * * * * * | - * - - - - - - | <-- |74160:10|QA
LC18 -> * * * * * * * - * * * | - * - - - - - - | <-- |74160:10|QB
LC20 -> * * * * * * * - - * * | - * - - - - - - | <-- |74160:10|QC
LC22 -> * * * * * * * - * - * | - * - - - - - - | <-- |74160:10|QD
Pin
4 -> * * * * * * * - - - - | - * - - - - - - | <-- BIN
83 -> - - - - - - - - - - - | - - - - - - - - | <-- CLK
1 -> - - - - - - - - - - - | - - - - - - - - | <-- CLRN
5 -> - - - - - - - * * * * | - * - - - - - - | <-- ENT
6 -> - - - - - - - * * * * | - * - - - - - - | <-- LDN
8 -> * * * * * * * - - - - | - * - - - - - - | <-- LTN
9 -> * * * * * * - - - - - | - * - - - - - - | <-- RBIN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex6.rpt
ex6
** EQUATIONS **
BIN : INPUT;
CLK : INPUT;
CLRN : INPUT;
ENT : INPUT;
LDN : INPUT;
LTN : INPUT;
RBIN : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', location is LC017, type is output.
A0 = LCELL( _EQ001 $ BIN);
_EQ001 = BIN & !_LC018 & !_LC020 & !_LC022 & _LC023 & LTN
# BIN & !_LC018 & !_LC020 & !_LC022 & LTN & !RBIN
# BIN & _LC018 & _LC022 & LTN
# BIN & _LC020 & !_LC023 & LTN;
-- Node name is 'A1'
-- Equation name is 'A1', location is LC019, type is output.
A1 = LCELL( _EQ002 $ BIN);
_EQ002 = BIN & !_LC018 & !_LC020 & !_LC022 & !_LC023 & LTN & !RBIN
# BIN & _LC018 & _LC020 & !_LC023 & LTN
# BIN & !_LC018 & _LC020 & _LC023 & LTN
# BIN & _LC018 & _LC022 & LTN;
-- Node name is 'A2'
-- Equation name is 'A2', location is LC021, type is output.
A2 = LCELL( _EQ003 $ BIN);
_EQ003 = BIN & !_LC020 & !_LC022 & !_LC023 & LTN & !RBIN
# BIN & _LC018 & !_LC020 & !_LC023 & LTN
# BIN & _LC020 & _LC022 & LTN;
-- Node name is 'A3'
-- Equation name is 'A3', location is LC024, type is output.
A3 = LCELL( _EQ004 $ BIN);
_EQ004 = BIN & !_LC018 & !_LC022 & !_LC023 & LTN & !RBIN
# BIN & _LC018 & _LC020 & _LC023 & LTN
# BIN & !_LC018 & _LC020 & !_LC023 & LTN
# BIN & !_LC018 & !_LC020 & _LC023 & LTN;
-- Node name is 'A4'
-- Equation name is 'A4', location is LC025, type is output.
A4 = LCELL( _EQ005 $ BIN);
_EQ005 = BIN & !_LC018 & !_LC020 & !_LC022 & LTN & !RBIN
# BIN & !_LC018 & _LC020 & LTN
# BIN & _LC023 & LTN;
-- Node name is 'A5'
-- Equation name is 'A5', location is LC027, type is output.
A5 = LCELL( _EQ006 $ BIN);
_EQ006 = BIN & !_LC020 & !_LC022 & _LC023 & LTN
# BIN & !_LC020 & !_LC022 & LTN & !RBIN
# BIN & _LC018 & _LC023 & LTN
# BIN & _LC018 & !_LC020 & LTN;
-- Node name is 'A6'
-- Equation name is 'A6', location is LC029, type is output.
A6 = LCELL( _EQ007 $ BIN);
_EQ007 = BIN & _LC018 & _LC020 & _LC023 & LTN
# BIN & !_LC018 & !_LC020 & !_LC022 & LTN;
-- Node name is '|74160:10|:6' = '|74160:10|QA'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ008 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ008 = !ENT & _LC023 & LDN
# ENT & !_LC023 & LDN;
-- Node name is '|74160:10|:7' = '|74160:10|QB'
-- Equation name is '_LC018', type is buried
_LC018 = TFFE( _EQ009, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ009 = ENT & !_LC018 & !_LC022 & _LC023 & LDN
# ENT & _LC018 & !_LC022 & _LC023
# _LC018 & !LDN;
-- Node name is '|74160:10|:8' = '|74160:10|QC'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _EQ010, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ010 = ENT & _LC018 & !_LC020 & _LC023 & LDN
# ENT & _LC018 & _LC020 & _LC023
# _LC020 & !LDN;
-- Node name is '|74160:10|:9' = '|74160:10|QD'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ011 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ011 = ENT & _LC018 & _LC020 & _LC023 & LDN
# !ENT & _LC022 & LDN
# _LC022 & !_LC023 & LDN;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\ex6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,730K
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