free_d.vhd

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-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity free_d is
 port(clk : in std_logic;
       s : out std_logic_vector(2 downto 0));
end;
architecture a of free_d is
signal reset : std_logic;
signal q : std_logic_vector(2 downto 0);
begin 
  process(clk)
   begin
     if reset='1'then
       q<="000";
     elsif clk'event and clk='1' then
        q<=q+1;
     end if;
    end process;
   ReSeT <= '1' WHEN Q=6  ELSE	  
		 '0';
   s<=q;
end a;