📄 ex10.rpt
字号:
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC19 H0
| +----------------------------- LC32 H1
| | +--------------------------- LC27 H2
| | | +------------------------- LC26 H3
| | | | +----------------------- LC21 H4
| | | | | +--------------------- LC18 H5
| | | | | | +------------------- LC25 |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node5
| | | | | | | +----------------- LC20 |LPM_ADD_SUB:279|addcore:adder|addcore:adder0|result_node5
| | | | | | | | +--------------- LC23 |LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | +------------- LC24 |LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | +----------- LC17 M0
| | | | | | | | | | | +--------- LC22 M1
| | | | | | | | | | | | +------- LC30 M2
| | | | | | | | | | | | | +----- LC31 M3
| | | | | | | | | | | | | | +--- LC29 M4
| | | | | | | | | | | | | | | +- LC28 M5
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> * * * * * * * - - - - - - - - - | - * | <-- H0
LC32 -> - * * * * * * - - - - - - - - - | - * | <-- H1
LC27 -> - - * * * * * - - - - - - - - - | - * | <-- H2
LC26 -> - - * * * * * - - - - - - - - - | - * | <-- H3
LC21 -> - - * * * * * - - - - - - - - - | - * | <-- H4
LC18 -> - - * * * * * - - - - - - - - - | - * | <-- H5
LC25 -> - - - - - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node5
LC20 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:279|addcore:adder|addcore:adder0|result_node5
LC17 -> * * * * * * - * - - * * * * * * | - * | <-- M0
LC22 -> * * * * * * - * - - - * * * * * | - * | <-- M1
LC30 -> * * * * * * - * - - - - * * * * | - * | <-- M2
LC31 -> * * * * * * - * - - - - * * * * | - * | <-- M3
LC29 -> * * * * * * - * - - - - * * * * | - * | <-- M4
LC28 -> * * * * * * - * - - - - * * * * | - * | <-- M5
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
LC3 -> * * * * * * - - * * * * * * * * | * * | <-- S0
LC7 -> * * * * * * - - * * * * * * * * | * * | <-- S1
LC1 -> * * * * * * - - * * * * * * * * | * * | <-- S2
LC2 -> * * * * * * - - * * * * * * * * | * * | <-- S3
LC5 -> * * * * * * - - * * * * * * * * | * * | <-- S4
LC6 -> * * * * * * - - - * * * * * * * | * * | <-- S5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex10.rpt
ex10
** EQUATIONS **
CLK : INPUT;
-- Node name is 'H0' = 'HOUR0'
-- Equation name is 'H0', location is LC019, type is output.
H0 = TFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 & !S2 & S3 & S4 &
S5;
-- Node name is 'H1' = 'HOUR1'
-- Equation name is 'H1', location is LC032, type is output.
H1 = TFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = H0 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 & !S2 & S3 &
S4 & S5;
-- Node name is 'H2' = 'HOUR2'
-- Equation name is 'H2', location is LC027, type is output.
H2 = TFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = H0 & H1 & !H2 & H5 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 &
S1 & !S2 & S3 & S4 & S5
# H0 & H1 & !H2 & H4 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 &
S1 & !S2 & S3 & S4 & S5
# H0 & H1 & !H2 & !H3 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 &
S1 & !S2 & S3 & S4 & S5
# H0 & H1 & H2 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 &
!S2 & S3 & S4 & S5;
-- Node name is 'H3' = 'HOUR3'
-- Equation name is 'H3', location is LC026, type is output.
H3 = TFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = H0 & H1 & !H2 & H3 & !H4 & !H5 & M0 & M1 & !M2 & M3 & M4 &
M5 & S0 & S1 & !S2 & S3 & S4 & S5
# H0 & H1 & H2 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 &
!S2 & S3 & S4 & S5;
-- Node name is 'H4' = 'HOUR4'
-- Equation name is 'H4', location is LC021, type is output.
H4 = TFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = H0 & H1 & H2 & H3 & !H4 & M0 & M1 & !M2 & M3 & M4 & M5 &
S0 & S1 & !S2 & S3 & S4 & S5 & _X001
# H0 & H1 & H2 & H3 & H4 & M0 & M1 & !M2 & M3 & M4 & M5 &
S0 & S1 & !S2 & S3 & S4 & S5;
_X001 = EXP( H0 & H1 & !H2 & H3 & !H5);
-- Node name is 'H5' = 'HOUR5'
-- Equation name is 'H5', location is LC018, type is output.
H5 = TFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = !H5 & _LC025 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 &
!S2 & S3 & S4 & S5 & _X002
# H5 & !_LC025 & M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 &
!S2 & S3 & S4 & S5;
_X002 = EXP( H0 & H1 & !H2 & H3 & !H4);
-- Node name is 'M0' = 'MIN0'
-- Equation name is 'M0', location is LC017, type is output.
M0 = TFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'M1' = 'MIN1'
-- Equation name is 'M1', location is LC022, type is output.
M1 = TFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = M0 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'M2' = 'MIN2'
-- Equation name is 'M2', location is LC030, type is output.
M2 = TFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = M0 & M1 & !M2 & !M5 & S0 & S1 & !S2 & S3 & S4 & S5
# M0 & M1 & !M2 & !M4 & S0 & S1 & !S2 & S3 & S4 & S5
# M0 & M1 & !M2 & !M3 & S0 & S1 & !S2 & S3 & S4 & S5
# M0 & M1 & M2 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'M3' = 'MIN3'
-- Equation name is 'M3', location is LC031, type is output.
M3 = TFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 & !S2 & S3 & S4 &
S5
# M0 & M1 & M2 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'M4' = 'MIN4'
-- Equation name is 'M4', location is LC029, type is output.
M4 = TFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 & !S2 & S3 & S4 &
S5
# M0 & M1 & M2 & M3 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'M5' = 'MIN5'
-- Equation name is 'M5', location is LC028, type is output.
M5 = TFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = M0 & M1 & !M2 & M3 & M4 & M5 & S0 & S1 & !S2 & S3 & S4 &
S5
# _LC020 & !M5 & S0 & S1 & !S2 & S3 & S4 & S5
# !_LC020 & M5 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'S0' = 'TEMP0'
-- Equation name is 'S0', location is LC003, type is output.
S0 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'S1' = 'TEMP1'
-- Equation name is 'S1', location is LC007, type is output.
S1 = TFFE( S0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'S2' = 'TEMP2'
-- Equation name is 'S2', location is LC001, type is output.
S2 = DFFE( _EQ013 $ _LC004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = _LC004 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'S3' = 'TEMP3'
-- Equation name is 'S3', location is LC002, type is output.
S3 = DFFE( _EQ014 $ _LC008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = _LC008 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'S4' = 'TEMP4'
-- Equation name is 'S4', location is LC005, type is output.
S4 = DFFE( _EQ015 $ _LC023, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = _LC023 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is 'S5' = 'TEMP5'
-- Equation name is 'S5', location is LC006, type is output.
S5 = DFFE( _EQ016 $ _LC024, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = _LC024 & S0 & S1 & !S2 & S3 & S4 & S5;
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( H5 $ _EQ017);
_EQ017 = H0 & H1 & H2 & H3 & H4;
-- Node name is '|LPM_ADD_SUB:279|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( M5 $ _EQ018);
_EQ018 = M0 & M1 & M2 & M3 & M4;
-- Node name is '|LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( S2 $ _EQ019);
_EQ019 = S0 & S1;
-- Node name is '|LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( S3 $ _EQ020);
_EQ020 = S0 & S1 & S2;
-- Node name is '|LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( S4 $ _EQ021);
_EQ021 = S0 & S1 & S2 & S3;
-- Node name is '|LPM_ADD_SUB:406|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( S5 $ _EQ022);
_EQ022 = S0 & S1 & S2 & S3 & S4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\ex10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,839K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -