📄 ex4.rpt
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Device-Specific Information: d:\vhdl_ex\ex4.rpt
ex4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC11 A0
| +----------- LC8 A1
| | +--------- LC3 A2
| | | +------- LC6 A3
| | | | +----- LC5 A4
| | | | | +--- LC16 A5
| | | | | | +- LC14 A6
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
22 -> * * * * * * * | * - - - - - - - | <-- BIN
83 -> - - - - - - - | - - - - - - - - | <-- CLK
1 -> - - - - - - - | - - - - - - - - | <-- CLRN
20 -> * * * * * * * | * - - - - - - - | <-- LTN
21 -> * * * * * * - | * - - - - - - - | <-- RBIN
LC115-> * * * * * * * | * - - - - - - * | <-- Q0
LC117-> * * * * * * * | * - - - - - - * | <-- Q1
LC118-> * * * * * * * | * - - - - - - * | <-- Q2
LC120-> * * * * * * * | * - - - - - - * | <-- Q3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex4.rpt
ex4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------- LC115 Q0
| +----- LC117 Q1
| | +--- LC118 Q2
| | | +- LC120 Q3
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'H'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC115-> * * * * | * - - - - - - * | <-- Q0
LC117-> - * * * | * - - - - - - * | <-- Q1
LC118-> - - * * | * - - - - - - * | <-- Q2
LC120-> - * - * | * - - - - - - * | <-- Q3
Pin
83 -> - - - - | - - - - - - - - | <-- CLK
1 -> - - - - | - - - - - - - - | <-- CLRN
6 -> * * * * | - - - - - - - * | <-- EN
18 -> * * * * | - - - - - - - * | <-- LDN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex4.rpt
ex4
** EQUATIONS **
BIN : INPUT;
CLK : INPUT;
CLRN : INPUT;
EN : INPUT;
LDN : INPUT;
LTN : INPUT;
RBIN : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', location is LC011, type is output.
A0 = LCELL( _EQ001 $ BIN);
_EQ001 = BIN & LTN & Q0 & !Q1 & !Q2 & !Q3
# BIN & LTN & !Q1 & !Q2 & !Q3 & !RBIN
# BIN & LTN & Q1 & Q3
# BIN & LTN & !Q0 & Q2;
-- Node name is 'A1'
-- Equation name is 'A1', location is LC008, type is output.
A1 = LCELL( _EQ002 $ BIN);
_EQ002 = BIN & LTN & !Q0 & !Q1 & !Q2 & !Q3 & !RBIN
# BIN & LTN & !Q0 & Q1 & Q2
# BIN & LTN & Q0 & !Q1 & Q2
# BIN & LTN & Q1 & Q3;
-- Node name is 'A2'
-- Equation name is 'A2', location is LC003, type is output.
A2 = LCELL( _EQ003 $ BIN);
_EQ003 = BIN & LTN & !Q0 & !Q2 & !Q3 & !RBIN
# BIN & LTN & !Q0 & Q1 & !Q2
# BIN & LTN & Q2 & Q3;
-- Node name is 'A3'
-- Equation name is 'A3', location is LC006, type is output.
A3 = LCELL( _EQ004 $ BIN);
_EQ004 = BIN & LTN & !Q0 & !Q1 & !Q3 & !RBIN
# BIN & LTN & Q0 & Q1 & Q2
# BIN & LTN & !Q0 & !Q1 & Q2
# BIN & LTN & Q0 & !Q1 & !Q2;
-- Node name is 'A4'
-- Equation name is 'A4', location is LC005, type is output.
A4 = LCELL( _EQ005 $ BIN);
_EQ005 = BIN & LTN & !Q1 & !Q2 & !Q3 & !RBIN
# BIN & LTN & !Q1 & Q2
# BIN & LTN & Q0;
-- Node name is 'A5'
-- Equation name is 'A5', location is LC016, type is output.
A5 = LCELL( _EQ006 $ BIN);
_EQ006 = BIN & LTN & Q0 & !Q2 & !Q3
# BIN & LTN & !Q2 & !Q3 & !RBIN
# BIN & LTN & Q0 & Q1
# BIN & LTN & Q1 & !Q2;
-- Node name is 'A6'
-- Equation name is 'A6', location is LC014, type is output.
A6 = LCELL( _EQ007 $ BIN);
_EQ007 = BIN & LTN & Q0 & Q1 & Q2
# BIN & LTN & !Q1 & !Q2 & !Q3;
-- Node name is 'Q0' = '|74160:12|QA'
-- Equation name is 'Q0', type is output
Q0 = DFFE( _EQ008 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ008 = !EN & LDN & Q0
# EN & LDN & !Q0;
-- Node name is 'Q1' = '|74160:12|QB'
-- Equation name is 'Q1', type is output
Q1 = TFFE( _EQ009, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ009 = EN & LDN & Q0 & !Q1 & !Q3
# EN & Q0 & Q1 & !Q3
# !LDN & Q1;
-- Node name is 'Q2' = '|74160:12|QC'
-- Equation name is 'Q2', type is output
Q2 = TFFE( _EQ010, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ010 = EN & LDN & Q0 & Q1 & !Q2
# EN & Q0 & Q1 & Q2
# !LDN & Q2;
-- Node name is 'Q3' = '|74160:12|QD'
-- Equation name is 'Q3', type is output
Q3 = DFFE( _EQ011 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ011 = EN & LDN & Q0 & Q1 & Q2
# !EN & LDN & Q3
# LDN & !Q0 & Q3;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\ex4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,231K
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