📄 addn.rpt
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Pin
4 -> * * - * * - * * * - * * * * - - | * * | <-- addend0
9 -> * * - * * - * * * - * * * * * - | * * | <-- addend1
14 -> * * - - - * - * * - * * * - * * | - * | <-- addend2
12 -> * * - - - - - - - * * * * * * * | - * | <-- addend3
6 -> * * - * * - * * * - * * * * - - | * * | <-- augend0
8 -> * * - * * - * * * - * * * * * - | * * | <-- augend1
11 -> * - - - - * * * * - * * * * * * | - * | <-- augend2
16 -> * - - - - - - - - * - - - - - - | - * | <-- augend3
5 -> * * - * - - * * * - * * * * - - | * * | <-- carry_in
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\gvhdl\addn.rpt
addn
** EQUATIONS **
addend0 : INPUT;
addend1 : INPUT;
addend2 : INPUT;
addend3 : INPUT;
augend0 : INPUT;
augend1 : INPUT;
augend2 : INPUT;
augend3 : INPUT;
carry_in : INPUT;
-- Node name is 'carry_out'
-- Equation name is 'carry_out', location is LC028, type is output.
carry_out = LCELL( _EQ001 $ GND);
_EQ001 = addend0 & augend0 & _X001 & _X002 & _X003
# carry_in & _X001 & _X002 & _X003 & _X004
# addend1 & augend1 & _X001 & _X003
# addend2 & augend2 & _X003
# addend3 & augend3;
_X001 = EXP(!addend2 & !augend2);
_X002 = EXP(!addend1 & !augend1);
_X003 = EXP(!addend3 & !augend3);
_X004 = EXP(!addend0 & !augend0);
-- Node name is 'overflow'
-- Equation name is 'overflow', location is LC030, type is output.
overflow = LCELL( _EQ002 $ _EQ003);
_EQ002 = addend0 & addend1 & addend2 & addend3 & augend0 & !_LC019 &
!_LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC024 & !_LC025
# addend1 & addend2 & addend3 & augend0 & carry_in & !_LC019 &
!_LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC024 & !_LC025
# addend0 & addend1 & addend2 & addend3 & carry_in & !_LC019 &
!_LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC024 & !_LC025
# addend0 & addend2 & addend3 & augend0 & augend1 & !_LC019 &
!_LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC024 & !_LC025;
_EQ003 = !_LC019 & !_LC020 & !_LC021 & !_LC022 & !_LC023 & !_LC024 &
!_LC025;
-- Node name is 'sum0'
-- Equation name is 'sum0', location is LC012, type is output.
sum0 = LCELL( _EQ004 $ carry_in);
_EQ004 = addend0 & !augend0
# !addend0 & augend0;
-- Node name is 'sum1'
-- Equation name is 'sum1', location is LC013, type is output.
sum1 = LCELL( _EQ005 $ addend1);
_EQ005 = addend0 & !augend1 & carry_in
# augend0 & !augend1 & _X005
# !addend0 & augend1 & _X006
# !augend0 & augend1 & !carry_in;
_X005 = EXP(!addend0 & !carry_in);
_X006 = EXP( augend0 & carry_in);
-- Node name is 'sum2'
-- Equation name is 'sum2', location is LC014, type is output.
sum2 = LCELL(!_LC029 $ _EQ006);
_EQ006 = !_LC026 & !_LC032;
-- Node name is 'sum3'
-- Equation name is 'sum3', location is LC031, type is output.
sum3 = LCELL(!_LC019 $ _EQ007);
_EQ007 = !_LC017 & !_LC018 & !_LC027;
-- Node name is '~171~1'
-- Equation name is '~171~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ008 $ GND);
_EQ008 = augend0 & augend1 & carry_in
# addend0 & augend1 & carry_in
# addend0 & augend0 & augend1
# addend1 & augend0 & carry_in
# addend0 & addend1 & carry_in;
-- Node name is '~171~2'
-- Equation name is '~171~2', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ009 $ GND);
_EQ009 = addend0 & addend1 & augend0
# addend1 & augend1;
-- Node name is '~171~3'
-- Equation name is '~171~3', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ010 $ GND);
_EQ010 = addend2 & !augend2
# !addend2 & augend2;
-- Node name is '~227~1'
-- Equation name is '~227~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ011 $ GND);
_EQ011 = augend0 & augend1 & augend2 & carry_in
# addend0 & augend1 & augend2 & carry_in
# addend0 & augend0 & augend1 & augend2
# addend1 & augend0 & augend2 & carry_in
# addend0 & addend1 & augend2 & carry_in;
-- Node name is '~227~2'
-- Equation name is '~227~2', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ012 $ GND);
_EQ012 = addend0 & addend1 & augend0 & augend2
# addend2 & augend0 & augend1 & carry_in
# addend0 & addend2 & augend1 & carry_in
# addend0 & addend2 & augend0 & augend1
# addend1 & addend2 & augend0 & carry_in;
-- Node name is '~227~3'
-- Equation name is '~227~3', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ013 $ GND);
_EQ013 = addend0 & addend1 & addend2 & carry_in
# addend0 & addend1 & addend2 & augend0
# addend1 & augend1 & augend2
# addend1 & addend2 & augend1
# addend2 & augend2;
-- Node name is '~227~4'
-- Equation name is '~227~4', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ014 $ GND);
_EQ014 = !addend3 & augend3
# addend3 & !augend3;
-- Node name is '~277~1'
-- Equation name is '~277~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ015 $ GND);
_EQ015 = addend2 & addend3 & augend0 & augend1 & carry_in
# addend0 & addend2 & addend3 & augend1 & carry_in
# addend0 & addend1 & addend3 & augend0 & augend2
# addend1 & addend3 & augend0 & augend2 & carry_in
# addend0 & addend1 & addend3 & augend2 & carry_in;
-- Node name is '~277~2'
-- Equation name is '~277~2', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ016 $ GND);
_EQ016 = addend0 & addend3 & augend0 & augend1 & augend2
# addend3 & augend0 & augend1 & augend2 & carry_in
# addend0 & addend3 & augend1 & augend2 & carry_in
# !addend0 & !addend1 & !addend2 & !addend3 & !augend0
# !addend0 & !addend1 & !addend2 & !addend3 & !carry_in;
-- Node name is '~277~3'
-- Equation name is '~277~3', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ017 $ GND);
_EQ017 = !addend1 & !addend2 & !addend3 & !augend0 & !carry_in
# !addend0 & !addend2 & !addend3 & !augend0 & !augend1
# !addend0 & !addend2 & !addend3 & !augend1 & !carry_in
# !addend2 & !addend3 & !augend0 & !augend1 & !carry_in
# !addend0 & !addend1 & !addend3 & !augend0 & !augend2;
-- Node name is '~277~4'
-- Equation name is '~277~4', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ018 $ GND);
_EQ018 = !addend0 & !addend1 & !addend3 & !augend2 & !carry_in
# !addend1 & !addend3 & !augend0 & !augend2 & !carry_in
# !addend0 & !addend3 & !augend0 & !augend1 & !augend2
# !addend0 & !addend3 & !augend1 & !augend2 & !carry_in
# !addend3 & !augend0 & !augend1 & !augend2 & !carry_in;
-- Node name is '~277~5'
-- Equation name is '~277~5', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ019 $ GND);
_EQ019 = addend1 & addend2 & addend3 & augend1
# addend1 & addend3 & augend1 & augend2
# !addend1 & !addend2 & !addend3 & !augend1
# !addend1 & !addend3 & !augend1 & !augend2
# addend2 & addend3 & augend2;
-- Node name is '~277~6'
-- Equation name is '~277~6', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ020 $ GND);
_EQ020 = !addend2 & !addend3 & !augend2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\gvhdl\addn.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,948K
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