373.vhd

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY 373 IS
 PORT (
       OEN,G : IN STD_LOGIC;
           D : IN STD_LOGIC_VECTOR(8 DOWNTO 1);
           Q : OUT IN STD_LOGICVECTOR(8 DOWNTO 1)
       );
END 373;
ARCHITECTURE A OF 373 IS
   COMPONENT LATCH
      	PORT(
   		           D,ENA : IN	STD_LOGIC;
   		                Q : OUT	STD_LOGIC
            );
   END COMPONENT;
   SIGNAL TEMP :STD_LOGIC(8 DOWNTO 1);
BEGIN
   GGLATCH:FOR I IN 1 TO 8 GENERATE
            GH:LATCH PORT MAP (D(I),G,TEMP(I));
   END GENERATE;
     Q<=TEMP WHEN OEN=0 ELSE
             "ZZZZZZZZ";
END A;