two_consecutive.vhd

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entity TWO_CONSECUTIVE is
  port(CLK,R,X: in BIT;Z: out BIT);
end TWO_CONSECUTIVE;

architecture DATAFLOW of TWO_CONSECUTIVE is
  signal Y1,Y0: BIT;
begin
  STATE: block((CLK = '1'and not CLK'STABLE) or R = '0')
  begin
    Y1 <= guarded '0' when R = '0' else X;
    Y0 <= guarded '0' when R = '0' else '1';
  end block STATE;
  Z <= Y0 and ((not Y1 and not X) or (Y1 and X));
end DATAFLOW;
           --   Behavioral description
--Figure 1.1

architecture ALGORITHMIC of TWO_CONSECUTIVE is
  type STATE is (S0,S1,S2);
  signal Q: STATE := S0;
begin
  process(R,X,CLK,Q)
  begin
    if (R'EVENT and R = '0') then --reset event
      Q <= S0;
    elsif (CLK'EVENT and CLK = '1') then --clock event
      if  X = '0' then
        Q <= S1;
      else
        Q <= S2;
      end if;
    end if;
    if Q'EVENT or X'EVENT then --output function
      if (Q=S1 and X='0') or (Q=S2 and X='1') then
        Z <= '1';
      else
        Z <= '0';
      end if;
    end if;
  end process;
end ALGORITHMIC;
--Figure 1.5. Algorithmic description of circuit from Figure 1.1.