📄 ex80.rpt
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ex80
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC27 Q0
| +----------------------------- LC24 Q1
| | +--------------------------- LC17 Q2
| | | +------------------------- LC29 Q3
| | | | +----------------------- LC23 Q4
| | | | | +--------------------- LC22 Q5
| | | | | | +------------------- LC21 Q6
| | | | | | | +----------------- LC18 Q7
| | | | | | | | +--------------- LC32 S0
| | | | | | | | | +------------- LC31 S1
| | | | | | | | | | +----------- LC28 S2
| | | | | | | | | | | +--------- LC30 S6
| | | | | | | | | | | | +------- LC20 |74161:1|p74161:sub|QD
| | | | | | | | | | | | | +----- LC19 |74161:1|p74161:sub|QC
| | | | | | | | | | | | | | +--- LC25 |74161:1|p74161:sub|QB
| | | | | | | | | | | | | | | +- LC26 |74161:1|p74161:sub|QA
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC27 -> * * - - - - - - - - - - * * * * | - * | <-- Q0
LC24 -> * - * - - - - - - - - - * * * * | - * | <-- Q1
LC17 -> * - - * - - - - - - - - * * * * | - * | <-- Q2
LC29 -> * - - - * - - - - - - - * * * * | - * | <-- Q3
LC23 -> * - - - - * - - - - - - * * * * | - * | <-- Q4
LC22 -> * - - - - - * - - - - - * * * * | - * | <-- Q5
LC21 -> * - - - - - - * - - - - * * * * | - * | <-- Q6
LC18 -> * - - - - - - - - - - - * * * * | - * | <-- Q7
LC20 -> - - - - - - - - * * * * * - - - | * * | <-- |74161:1|p74161:sub|QD
LC19 -> - - - - - - - - * * * * * * - - | * * | <-- |74161:1|p74161:sub|QC
LC25 -> - - - - - - - - * * * * * * * - | * * | <-- |74161:1|p74161:sub|QB
LC26 -> - - - - - - - - * * * * * * * * | * * | <-- |74161:1|p74161:sub|QA
Pin
5 -> - - - - - - - - * * * * - - - - | * * | <-- BIN
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
1 -> - - - - - - - - - - - - - - - - | - - | <-- CLRN
12 -> - - - - - - - - - - - - * * * * | - * | <-- CLRN1
14 -> - - - - - - - - - - - - - - - * | - * | <-- D0
17 -> - - - - - - - - - - - - - - * - | - * | <-- D1
11 -> - - - - - - - - - - - - - * - - | - * | <-- D2
16 -> - - - - - - - - - - - - * - - - | - * | <-- D3
9 -> - - - - - - - - - - - - * * * * | - * | <-- EN
8 -> - - - - - - - - - - - - * * * * | - * | <-- LDN
6 -> - - - - - - - - * * * * - - - - | * * | <-- LTN
4 -> - - - - - - - - * * * - - - - - | * * | <-- RBIN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex80.rpt
ex80
** EQUATIONS **
BIN : INPUT;
CLK : INPUT;
CLRN : INPUT;
CLRN1 : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
EN : INPUT;
LDN : INPUT;
LTN : INPUT;
RBIN : INPUT;
-- Node name is 'Q0' = '|74164:2|QA'
-- Equation name is 'Q0', type is output
Q0 = DFFE( _EQ001 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ001 = !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & !Q6 & !Q7;
-- Node name is 'Q1' = '|74164:2|QB'
-- Equation name is 'Q1', type is output
Q1 = DFFE( Q0 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q2' = '|74164:2|QC'
-- Equation name is 'Q2', type is output
Q2 = DFFE( Q1 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q3' = '|74164:2|QD'
-- Equation name is 'Q3', type is output
Q3 = DFFE( Q2 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q4' = '|74164:2|QE'
-- Equation name is 'Q4', type is output
Q4 = DFFE( Q3 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q5' = '|74164:2|QF'
-- Equation name is 'Q5', type is output
Q5 = DFFE( Q4 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q6' = '|74164:2|QG'
-- Equation name is 'Q6', type is output
Q6 = DFFE( Q5 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'Q7' = '|74164:2|QH'
-- Equation name is 'Q7', type is output
Q7 = DFFE( Q6 $ GND, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
-- Node name is 'S0'
-- Equation name is 'S0', location is LC032, type is output.
S0 = LCELL( _EQ002 $ BIN);
_EQ002 = BIN & !_LC019 & !_LC020 & !_LC025 & _LC026 & LTN
# BIN & !_LC019 & !_LC020 & !_LC025 & LTN & !RBIN
# BIN & _LC020 & _LC025 & LTN
# BIN & _LC019 & !_LC026 & LTN;
-- Node name is 'S1'
-- Equation name is 'S1', location is LC031, type is output.
S1 = LCELL( _EQ003 $ BIN);
_EQ003 = BIN & !_LC019 & !_LC020 & !_LC025 & !_LC026 & LTN & !RBIN
# BIN & _LC019 & _LC025 & !_LC026 & LTN
# BIN & _LC019 & !_LC025 & _LC026 & LTN
# BIN & _LC020 & _LC025 & LTN;
-- Node name is 'S2'
-- Equation name is 'S2', location is LC028, type is output.
S2 = LCELL( _EQ004 $ BIN);
_EQ004 = BIN & !_LC019 & !_LC020 & !_LC026 & LTN & !RBIN
# BIN & !_LC019 & _LC025 & !_LC026 & LTN
# BIN & _LC019 & _LC020 & LTN;
-- Node name is 'S3'
-- Equation name is 'S3', location is LC014, type is output.
S3 = LCELL( _EQ005 $ BIN);
_EQ005 = BIN & !_LC020 & !_LC025 & !_LC026 & LTN & !RBIN
# BIN & _LC019 & _LC025 & _LC026 & LTN
# BIN & _LC019 & !_LC025 & !_LC026 & LTN
# BIN & !_LC019 & !_LC025 & _LC026 & LTN;
-- Node name is 'S4'
-- Equation name is 'S4', location is LC015, type is output.
S4 = LCELL( _EQ006 $ BIN);
_EQ006 = BIN & !_LC019 & !_LC020 & !_LC025 & LTN & !RBIN
# BIN & _LC019 & !_LC025 & LTN
# BIN & _LC026 & LTN;
-- Node name is 'S5'
-- Equation name is 'S5', location is LC013, type is output.
S5 = LCELL( _EQ007 $ BIN);
_EQ007 = BIN & !_LC019 & !_LC020 & _LC026 & LTN
# BIN & !_LC019 & !_LC020 & LTN & !RBIN
# BIN & _LC025 & _LC026 & LTN
# BIN & !_LC019 & _LC025 & LTN;
-- Node name is 'S6'
-- Equation name is 'S6', location is LC030, type is output.
S6 = LCELL( _EQ008 $ BIN);
_EQ008 = BIN & _LC019 & _LC025 & _LC026 & LTN
# BIN & !_LC019 & !_LC020 & !_LC025 & LTN;
-- Node name is '|74161:1|p74161:sub|:9' = '|74161:1|p74161:sub|QA'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ009 $ GND, _EQ010, CLRN1, VCC, VCC);
_EQ009 = !EN & _LC026 & LDN
# EN & !_LC026 & LDN
# D0 & !LDN;
_EQ010 = !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & !Q6 & !Q7;
-- Node name is '|74161:1|p74161:sub|:8' = '|74161:1|p74161:sub|QB'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( _EQ011, _EQ012, CLRN1, VCC, VCC);
_EQ011 = EN & _LC026 & LDN
# D1 & !_LC025 & !LDN
# !D1 & _LC025 & !LDN;
_EQ012 = !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & !Q6 & !Q7;
-- Node name is '|74161:1|p74161:sub|:7' = '|74161:1|p74161:sub|QC'
-- Equation name is '_LC019', type is buried
_LC019 = TFFE( _EQ013, _EQ014, CLRN1, VCC, VCC);
_EQ013 = EN & _LC025 & _LC026 & LDN
# D2 & !_LC019 & !LDN
# !D2 & _LC019 & !LDN;
_EQ014 = !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & !Q6 & !Q7;
-- Node name is '|74161:1|p74161:sub|:6' = '|74161:1|p74161:sub|QD'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _EQ015, _EQ016, CLRN1, VCC, VCC);
_EQ015 = EN & _LC019 & _LC025 & _LC026 & LDN
# D3 & !_LC020 & !LDN
# !D3 & _LC020 & !LDN;
_EQ016 = !Q0 & !Q1 & !Q2 & !Q3 & !Q4 & !Q5 & !Q6 & !Q7;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\ex80.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,467K
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