📄 s373.rpt
字号:
| | | | | +--------- LC87 GH~99
| | | | | | +------- LC89 GH~111
| | | | | | | +----- LC91 GH~123
| | | | | | | | +--- LC93 Q1
| | | | | | | | | +- LC94 Q2
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC96 -> * - - - - - - - * - | - - - - - * - - | <-- GH
LC95 -> - * - - - - - - - * | - - - - - * - - | <-- GH~47
LC81 -> - - * - - - - - - - | - - - - - * * - | <-- GH~63
LC82 -> - - - * - - - - - - | - - - - - * * - | <-- GH~75
LC84 -> - - - - * - - - - - | - - - - - * * - | <-- GH~87
LC87 -> - - - - - * - - - - | - - - - - * * - | <-- GH~99
LC89 -> - - - - - - * - - - | - - - - - * * - | <-- GH~111
LC91 -> - - - - - - - * - - | - - - - - * * - | <-- GH~123
Pin
10 -> * - - - - - - - - - | - - - - - * - - | <-- D1
11 -> - * - - - - - - - - | - - - - - * - - | <-- D2
12 -> - - * - - - - - - - | - - - - - * - - | <-- D3
15 -> - - - * - - - - - - | - - - - - * - - | <-- D4
16 -> - - - - * - - - - - | - - - - - * - - | <-- D5
17 -> - - - - - * - - - - | - - - - - * - - | <-- D6
18 -> - - - - - - * - - - | - - - - - * - - | <-- D7
20 -> - - - - - - - * - - | - - - - - * - - | <-- D8
4 -> * * * * * * * * - - | - - - - - * - - | <-- G
84 -> - - - - - - - - * * | - - - - - * * - | <-- OEN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\s373.rpt
s373
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC97 Q3
| +--------- LC99 Q4
| | +------- LC101 Q5
| | | +----- LC104 Q6
| | | | +--- LC105 Q7
| | | | | +- LC107 Q8
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
84 -> * * * * * * | - - - - - * * - | <-- OEN
LC81 -> * - - - - - | - - - - - * * - | <-- GH~63
LC82 -> - * - - - - | - - - - - * * - | <-- GH~75
LC84 -> - - * - - - | - - - - - * * - | <-- GH~87
LC87 -> - - - * - - | - - - - - * * - | <-- GH~99
LC89 -> - - - - * - | - - - - - * * - | <-- GH~111
LC91 -> - - - - - * | - - - - - * * - | <-- GH~123
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\s373.rpt
s373
** EQUATIONS **
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
D8 : INPUT;
G : INPUT;
OEN : INPUT;
-- Node name is 'GH'
-- Equation name is 'GH', location is LC096, type is buried.
GH = LCELL( _EQ001 $ GND);
_EQ001 = D1 & G
# D1 & GH
# !G & GH;
-- Node name is 'GH~47'
-- Equation name is 'GH~47', location is LC095, type is buried.
GH~47 = LCELL( _EQ002 $ GND);
_EQ002 = D2 & G
# D2 & GH~47
# !G & GH~47;
-- Node name is 'GH~63'
-- Equation name is 'GH~63', location is LC081, type is buried.
GH~63 = LCELL( _EQ003 $ GND);
_EQ003 = D3 & G
# D3 & GH~63
# !G & GH~63;
-- Node name is 'GH~75'
-- Equation name is 'GH~75', location is LC082, type is buried.
GH~75 = LCELL( _EQ004 $ GND);
_EQ004 = D4 & G
# D4 & GH~75
# !G & GH~75;
-- Node name is 'GH~87'
-- Equation name is 'GH~87', location is LC084, type is buried.
GH~87 = LCELL( _EQ005 $ GND);
_EQ005 = D5 & G
# D5 & GH~87
# !G & GH~87;
-- Node name is 'GH~99'
-- Equation name is 'GH~99', location is LC087, type is buried.
GH~99 = LCELL( _EQ006 $ GND);
_EQ006 = D6 & G
# D6 & GH~99
# !G & GH~99;
-- Node name is 'GH~111'
-- Equation name is 'GH~111', location is LC089, type is buried.
GH~111 = LCELL( _EQ007 $ GND);
_EQ007 = D7 & G
# D7 & GH~111
# !G & GH~111;
-- Node name is 'GH~123'
-- Equation name is 'GH~123', location is LC091, type is buried.
GH~123 = LCELL( _EQ008 $ GND);
_EQ008 = D8 & G
# D8 & GH~123
# !G & GH~123;
-- Node name is 'Q1'
-- Equation name is 'Q1', location is LC093, type is output.
Q1 = TRI(_LC093, !OEN);
_LC093 = LCELL( _EQ009 $ GND);
_EQ009 = GH & !OEN;
-- Node name is 'Q2'
-- Equation name is 'Q2', location is LC094, type is output.
Q2 = TRI(_LC094, !OEN);
_LC094 = LCELL( _EQ010 $ GND);
_EQ010 = GH~47 & !OEN;
-- Node name is 'Q3'
-- Equation name is 'Q3', location is LC097, type is output.
Q3 = TRI(_LC097, !OEN);
_LC097 = LCELL( _EQ011 $ GND);
_EQ011 = GH~63 & !OEN;
-- Node name is 'Q4'
-- Equation name is 'Q4', location is LC099, type is output.
Q4 = TRI(_LC099, !OEN);
_LC099 = LCELL( _EQ012 $ GND);
_EQ012 = GH~75 & !OEN;
-- Node name is 'Q5'
-- Equation name is 'Q5', location is LC101, type is output.
Q5 = TRI(_LC101, !OEN);
_LC101 = LCELL( _EQ013 $ GND);
_EQ013 = GH~87 & !OEN;
-- Node name is 'Q6'
-- Equation name is 'Q6', location is LC104, type is output.
Q6 = TRI(_LC104, !OEN);
_LC104 = LCELL( _EQ014 $ GND);
_EQ014 = GH~99 & !OEN;
-- Node name is 'Q7'
-- Equation name is 'Q7', location is LC105, type is output.
Q7 = TRI(_LC105, !OEN);
_LC105 = LCELL( _EQ015 $ GND);
_EQ015 = GH~111 & !OEN;
-- Node name is 'Q8'
-- Equation name is 'Q8', location is LC107, type is output.
Q8 = TRI(_LC107, !OEN);
_LC107 = LCELL( _EQ016 $ GND);
_EQ016 = GH~123 & !OEN;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\s373.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,072K
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