📄 waveforms.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
package roms is
constant rom_width: integer:=4;
subtype rom_word is std_logic_vector(1 to rom_width);
subtype rom_range is integer range 0 to 12;
type rom_table is array(0 to 12) of rom_word;
constant rom:rom_table :=rom_table'(
"1100",
"1100",
"0100",
"0000",
"0110",
"0101",
"0111",
"1100",
"0100",
"0000",
"0110",
"0101",
"0111");
end roms
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.roms.ALL;
ENTITY wavefrom IS
PORT(clock: IN std_logic;
waves :out std_logic);
END ;
-----------------------------
ARCHITECTURE beh OF waveform IS
signal step: rom_range;
BEGIN
PROCESS(clock)
BEGIN
if (clock'event and clock='1')then
if step=rom_range'high then
step<=rom_range'low;
else
null;
step<=step+1;
end if;
end if;
end process;
waves<=rom(step);
end beh;
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