ex81.rpt

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        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC18 -> - - - - - - - * * - - - - - - - | - * | <-- ~217~1
LC20 -> - - - - - - * - - * - - - - - - | - * | <-- ~223~1
LC21 -> - - - - - * - - - - * - - - - - | - * | <-- ~229~1
LC22 -> - - - - * - - - - - - * - - - - | - * | <-- ~235~1
LC23 -> - - - * - - - - - - - - * - - - | - * | <-- ~241~1
LC24 -> - - * - - - - - - - - - - * - - | - * | <-- ~247~1
LC25 -> - * - - - - - - - - - - - - * - | - * | <-- ~253~1
LC27 -> * - - - - - - - - - - - - - - * | - * | <-- ~259~1

Pin
4    -> - - - - - - - - - - - - - - - * | - * | <-- D0
12   -> - - - - - - - - - - - - - - * - | - * | <-- D1
14   -> - - - - - - - - - - - - - * - - | - * | <-- D2
16   -> - - - - - - - - - - - - * - - - | - * | <-- D3
17   -> - - - - - - - - - - - * - - - - | - * | <-- D4
11   -> - - - - - - - - - - * - - - - - | - * | <-- D5
9    -> - - - - - - - - - * - - - - - - | - * | <-- D6
8    -> - - - - - - - - * - - - - - - - | - * | <-- D7
6    -> - - - - - - - - * * * * * * * * | - * | <-- G
5    -> * * * * * * * * - - - - - - - - | - * | <-- OEN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               d:\vhdl_ex\ex81.rpt
ex81

** EQUATIONS **

D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
D4       : INPUT;
D5       : INPUT;
D6       : INPUT;
D7       : INPUT;
G        : INPUT;
OEN      : INPUT;

-- Node name is 'Q0' 
-- Equation name is 'Q0', location is LC026, type is output.
Q0       = TRI(_LC026, !OEN);
_LC026   = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC027 & !OEN;

-- Node name is 'Q1' 
-- Equation name is 'Q1', location is LC028, type is output.
Q1       = TRI(_LC028, !OEN);
_LC028   = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC025 & !OEN;

-- Node name is 'Q2' 
-- Equation name is 'Q2', location is LC029, type is output.
Q2       = TRI(_LC029, !OEN);
_LC029   = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC024 & !OEN;

-- Node name is 'Q3' 
-- Equation name is 'Q3', location is LC030, type is output.
Q3       = TRI(_LC030, !OEN);
_LC030   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC023 & !OEN;

-- Node name is 'Q4' 
-- Equation name is 'Q4', location is LC019, type is output.
Q4       = TRI(_LC019, !OEN);
_LC019   = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC022 & !OEN;

-- Node name is 'Q5' 
-- Equation name is 'Q5', location is LC031, type is output.
Q5       = TRI(_LC031, !OEN);
_LC031   = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC021 & !OEN;

-- Node name is 'Q6' 
-- Equation name is 'Q6', location is LC032, type is output.
Q6       = TRI(_LC032, !OEN);
_LC032   = LCELL( _EQ007 $  GND);
  _EQ007 =  _LC020 & !OEN;

-- Node name is 'Q7' 
-- Equation name is 'Q7', location is LC017, type is output.
Q7       = TRI(_LC017, !OEN);
_LC017   = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC018 & !OEN;

-- Node name is '~217~1' 
-- Equation name is '~217~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ009 $  GND);
  _EQ009 =  D7 &  G
         # !G &  _LC018
         #  D7 &  _LC018;

-- Node name is '~223~1' 
-- Equation name is '~223~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ010 $  GND);
  _EQ010 =  D6 &  G
         # !G &  _LC020
         #  D6 &  _LC020;

-- Node name is '~229~1' 
-- Equation name is '~229~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ011 $  GND);
  _EQ011 =  D5 &  G
         # !G &  _LC021
         #  D5 &  _LC021;

-- Node name is '~235~1' 
-- Equation name is '~235~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ012 $  GND);
  _EQ012 =  D4 &  G
         # !G &  _LC022
         #  D4 &  _LC022;

-- Node name is '~241~1' 
-- Equation name is '~241~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ013 $  GND);
  _EQ013 =  D3 &  G
         # !G &  _LC023
         #  D3 &  _LC023;

-- Node name is '~247~1' 
-- Equation name is '~247~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ014 $  GND);
  _EQ014 =  D2 &  G
         # !G &  _LC024
         #  D2 &  _LC024;

-- Node name is '~253~1' 
-- Equation name is '~253~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ015 $  GND);
  _EQ015 =  D1 &  G
         # !G &  _LC025
         #  D1 &  _LC025;

-- Node name is '~259~1' 
-- Equation name is '~259~1', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ016 $  GND);
  _EQ016 =  D0 &  G
         # !G &  _LC027
         #  D0 &  _LC027;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\vhdl_ex\ex81.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,098K