ex71.tdf

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-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ex88 IS

	PORT
	(
		in1,in2	: STD_LOGIC_vector;
		pout		: OUT 	STD_LOGIC_vector
	);
	
END ex88;

ARCHITECTURE a OF ex88 IS

	SIGNAL	__count_signal_name	: INTEGER RANGE 0 TO __count_value;
	
BEGIN

	PROCESS (in1,in2)
	BEGIN	
       pout<=in1+in2 after 2ns;		
	END PROCESS;
END a;