moore1.rpt

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Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             d:\vhdl_ex\moore1.rpt
moore1

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (41)    17    B       TFFE   +  t        2      0   1    5    3    2    3  state~1
 (38)    20    B       TFFE   +  t        5      0   0    5    3    2    3  state~2
 (37)    21    B       DFFE   +  t        0      0   0    5    3    2    3  state~3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                             d:\vhdl_ex\moore1.rpt
moore1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                   Logic cells placed in LAB 'B'
        +--------- LC17 state~1
        | +------- LC20 state~2
        | | +----- LC21 state~3
        | | | +--- LC19 y0
        | | | | +- LC18 y1
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'B'
LC      | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * * * * * | - * | <-- state~1
LC20 -> * * * * * | - * | <-- state~2
LC21 -> * * * * * | - * | <-- state~3

Pin
43   -> - - - - - | - - | <-- clk
5    -> * * * - - | - * | <-- id0
8    -> * * * - - | - * | <-- id1
9    -> * * * - - | - * | <-- id2
6    -> * * * - - | - * | <-- id3
4    -> * * * - - | - * | <-- rst


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             d:\vhdl_ex\moore1.rpt
moore1

** EQUATIONS **

clk      : INPUT;
id0      : INPUT;
id1      : INPUT;
id2      : INPUT;
id3      : INPUT;
rst      : INPUT;

-- Node name is 'state~1' 
-- Equation name is 'state~1', location is LC017, type is buried.
state~1  = TFFE( _EQ001, GLOBAL( clk), !rst,  VCC,  VCC);
  _EQ001 =  id0 & !id1 & !id2 &  state~1 & !state~2 & !state~3
         # !id3 &  state~1 & !state~2 & !state~3 &  _X001
         # !rst & !state~1 & !state~2 &  state~3
         #  rst &  state~1 & !state~3;
  _X001  = EXP( id0 &  id1 &  id2);

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC020, type is buried.
state~2  = TFFE(!_EQ002, GLOBAL( clk), !rst,  VCC,  VCC);
  _EQ002 =  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X002  = EXP(!rst & !state~1 & !state~2 &  state~3);
  _X003  = EXP( id0 & !id1 & !id2 &  id3 & !rst &  state~1 & !state~2 & !state~3);
  _X004  = EXP( id0 &  id1 & !id2 &  id3 & !state~1 &  state~2 & !state~3);
  _X005  = EXP( rst &  state~2 & !state~3);
  _X006  = EXP( id0 &  id1 &  id2 & !id3 &  state~1 &  state~2 & !state~3);

-- Node name is 'state~3' 
-- Equation name is 'state~3', location is LC021, type is buried.
state~3  = DFFE( _EQ003 $  GND, GLOBAL( clk), !rst,  VCC,  VCC);
  _EQ003 =  id0 &  id1 & !id2 & !id3 & !rst & !state~1 & !state~2 & !state~3;

-- Node name is 'y0' 
-- Equation name is 'y0', location is LC019, type is output.
 y0      = LCELL( _EQ004 $  state~2);
  _EQ004 =  state~1 & !state~2 &  state~3;

-- Node name is 'y1' 
-- Equation name is 'y1', location is LC018, type is output.
 y1      = LCELL( _EQ005 $  VCC);
  _EQ005 = !state~1 & !state~2 & !state~3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                      d:\vhdl_ex\moore1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,662K