abc.rpt

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                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (38)    20    B       TFFE   +  t        0      0   0    0    0    7    3  |74162:11|QA (|74162:11|:43)
 (28)    28    B       TFFE   +  t        0      0   0    0    2    7    2  |74162:11|QB (|74162:11|:44)
 (29)    27    B       TFFE   +  t        0      0   0    0    2    7    1  |74162:11|QC (|74162:11|:45)
 (32)    25    B       DFFE   +  t        0      0   0    0    4    5    2  |74162:11|QD (|74162:11|:46)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                d:\vhdl_ex\abc.rpt
abc

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC22 q0
        | +--------------------- LC24 q1
        | | +------------------- LC17 q2
        | | | +----------------- LC19 q3
        | | | | +--------------- LC21 q4
        | | | | | +------------- LC18 q5
        | | | | | | +----------- LC23 q6
        | | | | | | | +--------- LC26 rb
        | | | | | | | | +------- LC20 |74162:11|QA
        | | | | | | | | | +----- LC28 |74162:11|QB
        | | | | | | | | | | +--- LC27 |74162:11|QC
        | | | | | | | | | | | +- LC25 |74162:11|QD
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC20 -> * * * * * * * - * * * * | - * | <-- |74162:11|QA
LC28 -> * * * * * * * - - * * * | - * | <-- |74162:11|QB
LC27 -> * * * * * * * - - - * * | - * | <-- |74162:11|QC
LC25 -> * * * - - * * - - * - * | - * | <-- |74162:11|QD

Pin
43   -> - - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                d:\vhdl_ex\abc.rpt
abc

** EQUATIONS **

clk      : INPUT;

-- Node name is 'q0' 
-- Equation name is 'q0', location is LC022, type is output.
 q0      = LCELL( _EQ001 $  VCC);
  _EQ001 =  _LC020 & !_LC025 & !_LC027 & !_LC028
         #  _LC025 &  _LC028
         # !_LC020 &  _LC027;

-- Node name is 'q1' 
-- Equation name is 'q1', location is LC024, type is output.
 q1      = LCELL( _EQ002 $  VCC);
  _EQ002 = !_LC020 &  _LC027 &  _LC028
         #  _LC020 &  _LC027 & !_LC028
         #  _LC025 &  _LC028;

-- Node name is 'q2' 
-- Equation name is 'q2', location is LC017, type is output.
 q2      = LCELL( _EQ003 $  VCC);
  _EQ003 = !_LC020 & !_LC027 &  _LC028
         #  _LC025 &  _LC027;

-- Node name is 'q3' 
-- Equation name is 'q3', location is LC019, type is output.
 q3      = LCELL( _EQ004 $ !_LC020);
  _EQ004 =  _LC020 & !_LC027 &  _LC028
         #  _LC027 & !_LC028;

-- Node name is 'q4' 
-- Equation name is 'q4', location is LC021, type is output.
 q4      = LCELL( _EQ005 $ !_LC020);
  _EQ005 = !_LC020 &  _LC027 & !_LC028;

-- Node name is 'q5' 
-- Equation name is 'q5', location is LC018, type is output.
 q5      = LCELL( _EQ006 $ !_LC028);
  _EQ006 =  _LC020 & !_LC025 & !_LC027 & !_LC028
         # !_LC020 &  _LC027 &  _LC028;

-- Node name is 'q6' 
-- Equation name is 'q6', location is LC023, type is output.
 q6      = LCELL( _EQ007 $  VCC);
  _EQ007 =  _LC020 &  _LC027 &  _LC028
         # !_LC025 & !_LC027 & !_LC028;

-- Node name is 'rb' 
-- Equation name is 'rb', location is LC026, type is output.
 rb      = LCELL( GND $  VCC);

-- Node name is '|74162:11|:43' = '|74162:11|QA' 
-- Equation name is '_LC020', type is buried 
_LC020   = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|74162:11|:44' = '|74162:11|QB' 
-- Equation name is '_LC028', type is buried 
_LC028   = TFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC020 & !_LC025;

-- Node name is '|74162:11|:45' = '|74162:11|QC' 
-- Equation name is '_LC027', type is buried 
_LC027   = TFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC020 &  _LC028;

-- Node name is '|74162:11|:46' = '|74162:11|QD' 
-- Equation name is '_LC025', type is buried 
_LC025   = DFFE( _EQ010 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC020 &  _LC027 &  _LC028
         # !_LC020 &  _LC025;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         d:\vhdl_ex\abc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,410K