ex5.rpt

大家一定要看 哦 程序在与多看多练 我找了好久才找到呢

! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                                d:\vhdl_ex\ex5.rpt
ex5

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  81    120    H     OUTPUT      t        0      0   0    0    3    0    0  count
  80    118    H         FF   +  t        0      0   0    2    3    5    0  Q0 (|74161:19|p74161:sub|:9)
  79    117    H         FF   +  t        0      0   0    2    3    5    0  Q1 (|74161:19|p74161:sub|:8)
  78    115    H         FF   +  t        0      0   0    2    3    5    0  Q2 (|74161:19|p74161:sub|:7)
  77    113    H         FF   +  t        0      0   0    2    4    1    0  Q3 (|74161:19|p74161:sub|:6)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                d:\vhdl_ex\ex5.rpt
ex5

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                   Logic cells placed in LAB 'H'
        +--------- LC120 count
        | +------- LC118 Q0
        | | +----- LC117 Q1
        | | | +--- LC115 Q2
        | | | | +- LC113 Q3
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'H'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC118-> * * * * * | - - - - - - - * | <-- Q0
LC117-> * * * * * | - - - - - - - * | <-- Q1
LC115-> * * * * * | - - - - - - - * | <-- Q2
LC113-> - - - - * | - - - - - - - * | <-- Q3

Pin
89   -> - - - - - | - - - - - - - - | <-- CLK
91   -> - - - - - | - - - - - - - - | <-- CLRN
100  -> - * - - - | - - - - - - - * | <-- D0
1    -> - - * - - | - - - - - - - * | <-- D1
2    -> - - - * - | - - - - - - - * | <-- D2
3    -> - - - - * | - - - - - - - * | <-- D3
4    -> - * * * * | - - - - - - - * | <-- EN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                d:\vhdl_ex\ex5.rpt
ex5

** EQUATIONS **

CLK      : INPUT;
CLRN     : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
EN       : INPUT;

-- Node name is 'count' 
-- Equation name is 'count', location is LC120, type is output.
 count   = LCELL( _EQ001 $  GND);
  _EQ001 = !Q0 &  Q1 &  Q2;

-- Node name is 'Q0' = '|74161:19|p74161:sub|QA' 
-- Equation name is 'Q0', type is output 
 Q0      = TFFE(!_EQ002, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);
  _EQ002 = !D0 & !Q0 &  Q1 &  Q2
         # !EN &  Q0
         # !EN & !Q2
         # !EN & !Q1;

-- Node name is 'Q1' = '|74161:19|p74161:sub|QB' 
-- Equation name is 'Q1', type is output 
 Q1      = TFFE( _EQ003, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);
  _EQ003 = !D1 & !Q0 &  Q1 &  Q2
         #  EN &  Q0;

-- Node name is 'Q2' = '|74161:19|p74161:sub|QC' 
-- Equation name is 'Q2', type is output 
 Q2      = TFFE( _EQ004, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);
  _EQ004 = !D2 & !Q0 &  Q1 &  Q2
         #  EN &  Q0 &  Q1;

-- Node name is 'Q3' = '|74161:19|p74161:sub|QD' 
-- Equation name is 'Q3', type is output 
 Q3      = TFFE( _EQ005, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);
  _EQ005 =  D3 & !Q0 &  Q1 &  Q2 & !Q3
         # !D3 & !Q0 &  Q1 &  Q2 &  Q3
         #  EN &  Q0 &  Q1 &  Q2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         d:\vhdl_ex\ex5.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 30,082K