📄 ex11.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EX11 IS
PORT (
G : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END EX11;
ARCHITECTURE A OF EX11 IS
SIGNAL TEMP :STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS
BEGIN
CASE D IS
WHEN "0000" => TEMP<="0111111"; ---- 0
WHEN "0001" => TEMP<="0000110"; ---- 1
WHEN "0010" => TEMP<="1011010"; ---- 2
WHEN "0011" => TEMP<="1001111"; ---- 3
WHEN "0100" => TEMP<="1100110"; ---- 4
WHEN "0101" => TEMP<="1101101"; ---- 5
WHEN "0110" => TEMP<="1111100"; ---- 6
WHEN "0111" => TEMP<="0000000"; ---- 7
WHEN "1000" => TEMP<="0000000"; ---- 8
WHEN "1001" => TEMP<="0000000"; ---- 9
WHEN "1010" => TEMP<="0110000"; ---- A
WHEN "1011" => TEMP<="0110000"; ---- B
WHEN "1100" => TEMP<="0110000"; ---- C
WHEN "1101" => TEMP<="0110000"; ---- D
WHEN "1110" => TEMP<="0110000"; ---- E
WHEN "1111" => TEMP<="0110000"; ---- F
WHEN OTHERS => TEMP<="0000000";
END CASE;
IF G='1' THEN
Q<=TEMP;
END IF;
END PROCESS;
END A;
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