ex2.vhd

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library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ex2 IS
		PORT(
		a       	: IN	STD_LOGIC;
		e       	: OUT	STD_LOGIC);
END ex2;
ARCHITECTURE a OF ex2 is
	SIGNAL temp : STD_LOGIC;
	BEGIN
	e <= not a ;  
END a;