seg471.vhd

来自「大家一定要看 哦 程序在与多看多练 我找了好久才找到呢」· VHDL 代码 · 共 37 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY SEG471 is
	PORT(
		  SEG		: OUT   STD_LOGIC_VECTOR(6 DOWNTO 0);	-- SEG7 Display O/P
	    -- SELOUT		: OUT   STD_LOGIC_VECTOR(5 DOWNTO 0);	-- Select SEG7 O/P	
		 NUM		: IN   STD_LOGIC_VECTOR(3 DOWNTO 0)	-- Number Display Signal	
		);
END;

ARCHITECTURE A OF SEG471 IS
BEGIN
SEVEN_SEGMENT : Block	-- Binary Code -> Segment 7 Code
Begin
		   --gfedcba
	SEG <= 	"0111111" WHEN NUM = 0 ELSE
		 	"0000110" WHEN NUM = 1 ELSE
 			"1011011" WHEN NUM = 2 ELSE
			"1001111" WHEN NUM = 3 ELSE
			"1100110" WHEN NUM = 4 ELSE
			"1101101" WHEN NUM = 5 ELSE
			"1111101" WHEN NUM = 6 ELSE
		 	"0000111" WHEN NUM = 7 ELSE
 			"1111111" WHEN NUM = 8 ELSE
			"1101111" WHEN NUM = 9 ELSE
			"0000000";
End Block SEVEN_SEGMENT;											
END a;