ex1.vhd

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library ieee;
use ieee.std_logic_1164.all;
entity ex1 is
port(a,w,c: in std_logic;
                q: out std_logic);
end ex1;
architecture rtl of ex1 is
signal data: std_logic_vector(1 downto 0);
begin 
  with data select
         q<= a when "00";
             w when "11";
             c when others; 
end rtl;