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        | | | | | | | | | | +----------- LC17 TEMP8
        | | | | | | | | | | | +--------- LC26 TEMP7
        | | | | | | | | | | | | +------- LC25 TEMP6
        | | | | | | | | | | | | | +----- LC23 TEMP5
        | | | | | | | | | | | | | | +--- LC18 TEMP4
        | | | | | | | | | | | | | | | +- LC22 TEMP3
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC30 -> - - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
LC29 -> - - - - - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
LC28 -> - - - - * - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
LC27 -> - - * * * * * * * * * * * * * * | - * | <-- TEMP14
LC32 -> - * * * * * * * * * * * * * * * | - * | <-- TEMP13
LC31 -> * * * * * * * * * * * * * * * * | - * | <-- TEMP12
LC21 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP11
LC20 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP10
LC19 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP9
LC17 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP8
LC26 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP7
LC25 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP6
LC23 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP5
LC18 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP4
LC22 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP3

Pin
43   -> - - - - - - - - - - - - - - - - | - - | <-- clk
LC13 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
LC12 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
LC8  -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
LC16 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
LC1  -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
LC2  -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
LC3  -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
LC7  -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
LC14 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
LC4  -> * * * * * * * * * * * * * * * * | * * | <-- TEMP2
LC5  -> * * * * * * * * * * * * * * * * | * * | <-- TEMP1
LC6  -> * * * * * * * * * * * * * * * * | * * | <-- TEMP0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  d:\mb\clkgen.rpt
clkgen

** EQUATIONS **

clk      : INPUT;

-- Node name is 'newclk' 
-- Equation name is 'newclk', location is LC024, type is output.
 newclk  = LCELL( _EQ001 $  GND);
  _EQ001 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & !TEMP6 & 
             !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 &  TEMP13 & 
              TEMP14;

-- Node name is ':17' = 'TEMP0' 
-- Equation name is 'TEMP0', location is LC006, type is buried.
TEMP0    = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':16' = 'TEMP1' 
-- Equation name is 'TEMP1', location is LC005, type is buried.
TEMP1    = TFFE( TEMP0, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':15' = 'TEMP2' 
-- Equation name is 'TEMP2', location is LC004, type is buried.
TEMP2    = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  TEMP0 &  TEMP1;

-- Node name is ':14' = 'TEMP3' 
-- Equation name is 'TEMP3', location is LC022, type is buried.
TEMP3    = DFFE( _EQ003 $  _LC013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  _LC013 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':13' = 'TEMP4' 
-- Equation name is 'TEMP4', location is LC018, type is buried.
TEMP4    = DFFE( _EQ004 $  _LC012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  _LC012 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':12' = 'TEMP5' 
-- Equation name is 'TEMP5', location is LC023, type is buried.
TEMP5    = DFFE( _EQ005 $  _LC008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  _LC008 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':11' = 'TEMP6' 
-- Equation name is 'TEMP6', location is LC025, type is buried.
TEMP6    = DFFE( _EQ006 $  _LC016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC016 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':10' = 'TEMP7' 
-- Equation name is 'TEMP7', location is LC026, type is buried.
TEMP7    = DFFE( _EQ007 $  _LC001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC001 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':9' = 'TEMP8' 
-- Equation name is 'TEMP8', location is LC017, type is buried.
TEMP8    = DFFE( _EQ008 $  _LC002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC002 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':8' = 'TEMP9' 
-- Equation name is 'TEMP9', location is LC019, type is buried.
TEMP9    = DFFE( _EQ009 $  _LC003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC003 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':7' = 'TEMP10' 
-- Equation name is 'TEMP10', location is LC020, type is buried.
TEMP10   = DFFE( _EQ010 $  _LC007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC007 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':6' = 'TEMP11' 
-- Equation name is 'TEMP11', location is LC021, type is buried.
TEMP11   = DFFE( _EQ011 $  _LC014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  _LC014 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':5' = 'TEMP12' 
-- Equation name is 'TEMP12', location is LC031, type is buried.
TEMP12   = DFFE( _EQ012 $  _LC030, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC030 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':4' = 'TEMP13' 
-- Equation name is 'TEMP13', location is LC032, type is buried.
TEMP13   = DFFE( _EQ013 $  _LC029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC029 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is ':3' = 'TEMP14' 
-- Equation name is 'TEMP14', location is LC027, type is buried.
TEMP14   = DFFE( _EQ014 $  _LC028, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC028 &  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 & !TEMP4 &  TEMP5 & 
             !TEMP6 & !TEMP7 &  TEMP8 & !TEMP9 &  TEMP10 & !TEMP11 &  TEMP12 & 
              TEMP13 &  TEMP14;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried 
_LC013   = LCELL( TEMP3 $  _EQ015);
  _EQ015 =  TEMP0 &  TEMP1 &  TEMP2;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried 
_LC012   = LCELL( TEMP4 $  _EQ016);
  _EQ016 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried 
_LC008   = LCELL( TEMP5 $  _EQ017);
  _EQ017 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC016', type is buried 
_LC016   = LCELL( TEMP6 $  _EQ018);
  _EQ018 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC001', type is buried 
_LC001   = LCELL( TEMP7 $  _EQ019);
  _EQ019 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried 
_LC002   = LCELL( TEMP8 $  _EQ020);
  _EQ020 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC003', type is buried 
_LC003   = LCELL( TEMP9 $  _EQ021);
  _EQ021 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC007', type is buried 
_LC007   = LCELL( TEMP10 $  _EQ022);
  _EQ022 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8 &  TEMP9;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC014', type is buried 
_LC014   = LCELL( TEMP11 $  _EQ023);
  _EQ023 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8 &  TEMP9 &  TEMP10;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( TEMP12 $  _EQ024);
  _EQ024 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8 &  TEMP9 &  TEMP10 &  TEMP11;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( TEMP13 $  _EQ025);
  _EQ025 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8 &  TEMP9 &  TEMP10 &  TEMP11 &  TEMP12;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( TEMP14 $  _EQ026);
  _EQ026 =  TEMP0 &  TEMP1 &  TEMP2 &  TEMP3 &  TEMP4 &  TEMP5 &  TEMP6 & 
              TEMP7 &  TEMP8 &  TEMP9 &  TEMP10 &  TEMP11 &  TEMP12 &  TEMP13;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                           d:\mb\clkgen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,219K

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