cnt6.rpt

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Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    d:\mb\cnt6.rpt
cnt6

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (38)    20    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    d:\mb\cnt6.rpt
cnt6

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                     Logic cells placed in LAB 'B'
        +----------- LC22 cARRY_OUT
        | +--------- LC21 CQ0
        | | +------- LC19 CQ1
        | | | +----- LC18 CQ2
        | | | | +--- LC17 CQ3
        | | | | | +- LC20 |LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'B'
LC      | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * * * * * * | - * | <-- CQ0
LC19 -> * - * * * * | - * | <-- CQ1
LC18 -> * - * * * * | - * | <-- CQ2
LC17 -> * - * * * * | - * | <-- CQ3
LC20 -> - - - - * - | - * | <-- |LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3

Pin
43   -> - - - - - - | - - | <-- clk
1    -> - - - - - - | - - | <-- clr
4    -> * * * * * - | - * | <-- ENA


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    d:\mb\cnt6.rpt
cnt6

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
ENA      : INPUT;

-- Node name is 'cARRY_OUT' 
-- Equation name is 'cARRY_OUT', location is LC022, type is output.
 cARRY_OUT = LCELL( _EQ001 $  GND);
  _EQ001 =  CQ0 & !CQ1 &  CQ2 & !CQ3 &  ENA;

-- Node name is 'CQ0' = ':10' 
-- Equation name is 'CQ0', type is output 
 CQ0     = TFFE( ENA, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);

-- Node name is 'CQ1' = ':8' 
-- Equation name is 'CQ1', type is output 
 CQ1     = TFFE( _EQ002, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ002 =  CQ0 & !CQ1 &  CQ3 &  ENA
         #  CQ0 & !CQ1 & !CQ2 &  ENA
         #  CQ0 &  CQ1 &  ENA;

-- Node name is 'CQ2' = ':6' 
-- Equation name is 'CQ2', type is output 
 CQ2     = TFFE( _EQ003, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ003 =  CQ0 & !CQ1 &  CQ2 & !CQ3 &  ENA
         #  CQ0 &  CQ1 &  ENA;

-- Node name is 'CQ3' = ':4' 
-- Equation name is 'CQ3', type is output 
 CQ3     = DFFE( _EQ004 $  _LC020, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ004 =  CQ0 & !CQ1 &  CQ2 & !CQ3 &  _LC020
         #  CQ3 & !ENA & !_LC020
         # !CQ3 & !ENA &  _LC020;

-- Node name is '|LPM_ADD_SUB:74|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( CQ3 $  _EQ005);
  _EQ005 =  CQ0 &  CQ1 &  CQ2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                             d:\mb\cnt6.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,195K