we2.vhd

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library ieee;
use ieee.std_logic_1164.all;
package mypack1 is 
function minium (a,b:in std_logic_vector)
return std_logic_vector;
end mypack1;
package body mypack1 is
function minium (a,b:in std_logic_vector)
return std_logic_vector is
begin
if a<b then
    return a;
else
return b;
end if;
end minium;
end mypack1;

library ieee;
use ieee.std_logic_1164.all;
use work.mypack1.all;
entity we2 is
port (d1,d2:in std_logic;
         q:out std_logic);
end;
architecture behave of we2 is
begin
q<=minium (d1,d2);
end;