saos.vhd
来自「大家一定要看 哦 程序在与多看多练 我找了好久才找到呢」· VHDL 代码 · 共 71 行
VHD
71 行
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY saos IS
PORT(
clk : IN STD_LOGIC;
p1,p2,p3,p4,p5,p6,p7,p8 : IN STD_LOGIC_VECTOR(3 downto 0);
choice : OUT STD_LOGIC_VECTOR(7 downto 0);
data : OUT STD_LOGIC_VECTOR(7 downto 0));
END saos;
ARCHITECTURE a OF saos IS
SIGNAL count : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL temp : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL choicein, datain : STD_LOGIC_VECTOR(7 downto 0);
BEGIN
clk1_label:
PROCESS (clk)
BEGIN
IF clk'event and clk='1' THEN
count<=count+1;
END IF;
END PROCESS clk1_label;
clk2_label:
PROCESS (clk)
BEGIN
if clk'event and clk='0' then
choice<=choicein;
data<=datain;
END IF;
END PROCESS clk2_label;
choicein<="00000001" when count="000" else
"00000010" when count="001" else
"00000100" when count="010" else
"00001000" when count="011" else
"00010000" when count="100" else
"00100000" when count="101" else
"01000000" when count="110" else
"10000000" ;
temp<= p1(3 downto 0) when count="000" else
p2(3 downto 0) when count="001" else
p3(3 downto 0) when count="010" else
p4(3 downto 0) when count="011" else
p5(3 downto 0) when count="100" else
p6(3 downto 0) when count="101" else
p7(3 downto 0) when count="110" else
p8(3 downto 0) ;
WITH temp select
datain <= "11111100" WHEN "0000",
"01100000" WHEN "0001",
"11011010" WHEN "0010",
"11110010" WHEN "0011",
"01100110" WHEN "0100",
"10110110" WHEN "0101",
"10111110" WHEN "0110",
"11100000" WHEN "0111",
"11111110" WHEN "1000",
"11110110" WHEN "1001",
"11101110" WHEN "1010",
"00111110" WHEN "1011",
"10011100" WHEN "1100",
"01111010" WHEN "1101",
"10011110" WHEN "1110",
"10001110" WHEN OTHERS;
END a;
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