fir_fr32.asm

blankfin 中对iir功能进行测试

/*******************************************************************************
Copyright(c) 2000 - 2003 Analog Devices. All Rights Reserved.
Developed by Blackfin DSP software Group, IPDC, Bangalore, India
for Blackfin DSPs.
By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software. 
********************************************************************************  
Module name     :   fir_fr32.asm
Label name      :   __fir_fr32
Version         :   1.1

Change History  :
                Version     Date        Author          Comments
                1.1         02/17/2003  Swarnalatha     Tested with
                                                        VDSP++ 3.0 on 
                                                        ADSP-21535 Rev.0.2
                1.0         12/17/2000 Manoj&Siva       Original
                                
Description     :   This program implements a T tap FIR filtering for 1.31 format
                    data and coefficients.
					 
	
Implementation  :    (d.h*c.h) + ((d.h*c.l+c.h*d.l)+(d.l*c.l)>>16) >>> 16, 
                    where d is data and c is the coefficient
Prototype       :
                    Void _fir_fr32
                            (
                            fract32 *,      //Pointer to the input
                            fract32 *,      //Pointer to the output
                            fract32 *,      //Pointer to the coefficients
                            fract32 *,      //Pointer to the delay line
                            int,            //Number of coefficients
                            int,            //Number of samples
                            fract32 *       //Read write pointer
                            )
Registers used  :   A0, A1, R0-R3, I0-I3, B1-B3, L1-L3, P0-P2, LC0, LC1
                            
                    
Performance     :
                    Initializations : 28 Cycles
                    Core Cycle Count: N*(3*T + 5)  Cycles
                    where N is the number of data samples
                    For N=128, T=8 Cycle count=4412 cycles
*******************************************************************************/   
.section L1_code;
.align 8;
.global    __fir_fr32;


__fir_fr32 :
    
    I0=R0; 			        // ADDRESS OF INPUT ARRAY  
	I3=R1;  		        // ADDRESS OF OUTPUT ARRAY
	B3=R1;
    I2=R2;                  // POINTER TO FILTER COEFFICIENTS
    B2=R2;
    P2=[SP+12];             // POINTER TO DELAY LINE BUFFER
	MNOP ||R1=[SP+16];      // NUMBER OF FILTER COEFFICIENTS 
	P0=[SP+20];             // NUMBER OF INPUT SAMPLES
    P1=[SP+24];       	    // ARRDESS OF READ WRITE POINTER
	B1=P2;				    // INITIALISE B1 AND L1 
   	I1=P2;     			    // INDEX TO READ/WRITE POINTER

    R3=R1<<2;               // EACH COEFFICIENT IS OF 32 BIT FETCH
	R0=P0;
	R0=R0 << 2 || NOP;

	L1=R3;      		    // FOR  DELAY LINE CIRCULAR BUFFER
    L2=R3;
	L3=R0;
	R1+=-1;
   	P2=R1;                  //INNER LOOP COUNT TO NUMBER OF FILTER COEFFICIENTS
 	R3=R3-R3 (S) || R0=[I0++] || I3-=4;
   	L0=0;	
   	[I1--]=R0||R1=[I2++];   //FETCH INPUT AND FILTER COEFF.


	LSETUP(FIR_START,FIR_END)LC0=P0;
	                        //LOOP SETUP FOR NUMBER OF INPUT SAMPLES
FIR_START:
	    LSETUP(M_ST,M_ST) LC1=P2;
	                        //LOOP SETUP FOR NUMBER OF FILTER COEFFS
	        A0=R0.L*R1.L (FU) || R0=[I1--] || R1=[I2++];
	        
M_ST:       R3.L=(A0+=R0.L*R1.L) (FU) || R0=[I1--] || R1=[I2++];

	    A1=R3 || NOP;

	    A0=R0.H*R1.H , A1+=R0.H*R1.L (M) ||[I3++]=R2;
	    LSETUP(MAC_ST,MAC_END)LC1=P2;
	                        //LOOP SETUP FOR NUMBER OF FILTER COEFFS
MAC_ST:	    A1+=R1.H*R0.L (M) || R0=[I1--] || R1=[I2++];
MAC_END:    R2=(A0+=R0.H*R1.H) , A1+=R0.H*R1.L (M);

		R3=(A1+=R1.H*R0.L) (M) || I1+=4 ||  R0=[I0++]; 
		R3=R3>>>15 ||[I1--]=R0 || R1=[I2++];
		
FIR_END:R2=R2+R3 (S);

		[I3++]=R2;
		L1=0;
		L2=0;
		L3=0;
		RTS;