adsp-21535_asm.ldf

blankfin 的 dma 驱动控制代码

ARCHITECTURE(ADSP-BF535)
SEARCH_DIR( $ADI_DSP\blackfin\lib )

$OBJECTS = $COMMAND_LINE_OBJECTS;
//$LIBRARIES = librt.dlb;
$LIBRARIES = $COMMAND_LINE_OBJECTS;

/*
** Memory map.
** 
** The known memory spaces are as follows:
** 
** 0xFFE00000 - 0xFFFFFFFF		Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF		System MMR registers (2MB)
** 0xFFB04000 - 0xFFBFFFFF		Reserved
** 0xFFB00000 - 0xFFB03FFF		Scratch SRAM (16K)
** 0xFFA04000 - 0xFFAFFFFF		Reserved
** 0xFFA00000 - 0xFFA03FFF		Code SRAM (16K)
** 0xFF904000 - 0xFF9FFFFF		Reserved
** 0xFF900000 - 0xFF903FFF		Data Bank B SRAM (16K)
** 0xFF804000 - 0xFF8FFFFF		Reserved
** 0xFF800000 - 0xFF803FFF		Data Bank A SRAM (16K)
** 0xF0040000 - 0xFF7FFFFF		Reserved RAM
** 0xF0000000 - 0xF003FFFF		L2 SRAM (256K)
** 0xEF000400 - 0xEFFFFFFF		Reserved ROM
** 0xEF000000 - 0xEF0003FF		Boot ROM (1K)
** 0x00000000 - 0xEEFFFFFF		unpopulated
*/

MEMORY
{
	/** Memory Mapped Registers **/
	//CORE_MMR	{ TYPE(RAM) START(0xFFE00000) END(0xFFFFFFFF) WIDTH(8) }	// the linker does not allow core MMR space to be defined
	//SYS_MMR		{ TYPE(RAM) START(0xFFC00000) END(0xFFDFFFFF) WIDTH(8) }	// should the linker yell about defining the SYS_MMR space too?
	
	/** Level 1 Memory **/
	SCRATCH		{ TYPE(RAM) START(0xFFB00000) END(0xFFB03FFF) WIDTH(8) }
	CODE		{ TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) }

	//DATA_B		{ TYPE(RAM) START(0xFF900000) END(0xFF903FFF) WIDTH(8) }
	DATA_B_0	{ TYPE(RAM) START(0xFF900000) END(0xFF900FFF) WIDTH(8) }	// super-bank B, mini-bank 0
	DATA_B_1	{ TYPE(RAM) START(0xFF901000) END(0xFF901FFF) WIDTH(8) }	// super-bank B, mini-bank 1
	DATA_B_2	{ TYPE(RAM) START(0xFF902000) END(0xFF902FFF) WIDTH(8) }	// super-bank B, mini-bank 2
	DATA_B_3	{ TYPE(RAM) START(0xFF903000) END(0xFF903FFF) WIDTH(8) }	// super-bank B, mini-bank 3
	
	//DATA_A		{ TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }
	DATA_A_0	{ TYPE(RAM) START(0xFF800000) END(0xFF800FFF) WIDTH(8) }	// super-bank A, mini-bank 0
	DATA_A_1	{ TYPE(RAM) START(0xFF801000) END(0xFF801FFF) WIDTH(8) }	// super-bank A, mini-bank 1
	DATA_A_2	{ TYPE(RAM) START(0xFF802000) END(0xFF802FFF) WIDTH(8) }	// super-bank A, mini-bank 2
	DATA_A_3	{ TYPE(RAM) START(0xFF803000) END(0xFF803FFF) WIDTH(8) }	// super-bank A, mini-bank 3
	
	/** Level 2 Memory **/
	L2_BANK0	{ TYPE(RAM) START(0xF0000000) END(0xF0007FFF) WIDTH(8) }
	L2_BANK1	{ TYPE(RAM) START(0xF0008000) END(0xF000FFFF) WIDTH(8) }
	L2_BANK2	{ TYPE(RAM) START(0xF0010000) END(0xF0017FFF) WIDTH(8) }
	L2_BANK3	{ TYPE(RAM) START(0xF0018000) END(0xF001FFFF) WIDTH(8) }
	L2_BANK4	{ TYPE(RAM) START(0xF0020000) END(0xF0027FFF) WIDTH(8) }
	L2_BANK5	{ TYPE(RAM) START(0xF0028000) END(0xF002FFFF) WIDTH(8) }
	L2_BANK6	{ TYPE(RAM) START(0xF0030000) END(0xF0037FFF) WIDTH(8) }
	L2_BANK7	{ TYPE(RAM) START(0xF0038000) END(0xF003FFFF) WIDTH(8) }

	/** The space for the on-chip ROM **/
//	BOOT_ROM	{ TYPE(RAM) START(0xEF000000) END(0xEF0003FF) WIDTH(8) }
}

PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

    SECTIONS
    {
		/* Stack */
		stack
		{
			INPUT_SECTION_ALIGN(2)
			INPUT_SECTIONS( $OBJECTS(ustack))
		}>SCRATCH

		/* code */
        code
        {
        	INPUT_SECTION_ALIGN(2)	// align all code sections on 2 byte boundary
        	INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program) )
		}>CODE

		start_code
		{
			INPUT_SECTION_ALIGN(2)
			INPUT_SECTIONS( $OBJECTS(start_from_here))
		}>L2_BANK0

		/* L1  A bank data memory */
        L1_A0
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L1_A0_data) )
		}>DATA_A_0        

		L1_A1
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L1_A1_data) )
		}>DATA_A_1 
       

		
        /* L1 B bank data memory */
        L1_B0
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L1_B0_data) )
		}>DATA_B_0        

		L1_B1
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L1_B1_data) )
		}>DATA_B_1
      
 
		L2_B2
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L2_B2_data) )
		}>L2_BANK2

		L2_B3
        {
        	INPUT_SECTION_ALIGN(2)	
        	INPUT_SECTIONS( $OBJECTS(L2_B3_data) )
		}>L2_BANK3 
		 
		/*
		data_b
        {
        	INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(data_b) $LIBRARIES(data_b) )
		}>DATA_B_1 
		*/
		l2_bank0
		{
		    INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(l2_bank0) $LIBRARIES(l2_bank0) )
		}>L2_BANK0
		
		l2_bank1
		{
		    INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(l2_bank1) $LIBRARIES(l2_bank1) )
		}>L2_BANK1
    }
}